8086/8088 system structure of Microprocessor

I. Basic architecture of 8086/8088 Microprocessor 

Intel 8086 Microprocessor has 16-bit registers and 16-bit external data bus, 20-bit address bus, addressing 1 MB address space. The external data bus of Intel 8088 microprocessor is 8-bit, and the others are the same as those of 8086.

 

 

Figure 1 8086 structure of the microprocessor

 

It can be seen that the 8086 CPU is divided into two functional parts: Bus Interface Unit (BIU) and Execution Unit (EU ).

As a bus control unit, Biu is responsible for transmitting data with memory and IO interfaces; EU is also responsible for executing commands. Specifically, Biu sends the commands to the queue of the instruction stream based on the request of the EU to provide the instructions to be executed for the EU. The instructions and data obtained by the EU from the instruction queue of The BIU are as follows, to access the operation outside the credit card (outside the credit card refers to the place where data is stored outside the CPU, such as memory and I/O interface. In this way, the EU and Biu can work independently, while the BIU can perform command prefetch while ensuring the operation Number of the EU and the off-chip transmission, which can overlap with the EU. The fetch part and the execution part can be separated to improve the CPU utilization. (2 NULL bytes appear in the 8086 command queue, and the EU does not occupy the bus, Biu automatically takes the command to fill the queue .)

EU components: 16-bit general register group (ax, BX, CX, dx, SP, BP, Si, DI), arithmetic logic unit (ALU), flag) and Operation controller circuit.

Biu components: segment register group (CS, DS, SS, ES), instruction pointer (IP), address divider, instruction queue buffer, bus interface control logic.

The following describes the components of EU:

1. 16-bit general register group (ax, BX, CX, dx, SP, BP, Si, DI)

(1) Four 16-bit general data registers: ax, BX, CX, dx, and can be divided into two eight-bit registers: al, ah, BL, BH, Cl, CH, DL, DH

Where:

Ax: Has the accumulate function. It can be used as a 16-bit accumulators, and Al can be used as an 8-bit accumulators.

Bx: acts as the base address register when the base address is changed.

CX: Used as the default counter register when executing loop and string processing commands.

DX: Used as a data register to store high 16-bit data in dual-word operations.

(2) Four other address pointers and address change registers

SP (Stack pointer): A stack pointer register used to indicate the top offset address of the stack.

BP (base pointer): base address pointer register, used as the base address register for indirect addressing.

Si (source index): Source Address Change register, which acts as an address register or address change register in indirect addressing. In the string processing instruction, it is used as the destination address change register.

Di (destination index): the destination address register, used as the address register or address change register in indirect addressing. In the string processing instruction, it is used as the source address register.

2. arithmetic logical unit (ALU)

It mainly performs arithmetic and logical operations.

3. Flag (FLAG) [1]

It is a 16-bit register used to record the status information of running results in the program. They are automatically set by the CPU Based on the running results of the relevant commands. The nine digits are defined. The six digits in the nine digits represent the State, and the three digits represent the control flag, as shown in Figure 2:

Figure 2 flag)

 

(1) carry mark (CF): after an operation command is executed, if carry or borrow bits are generated on the highest bit, this flag is set to 1. Specifically, when two numbers are added, the highest bit (D15 or D7) has an increment, or when two numbers are subtracted, the highest bit has a borrow bit, and the carry flag is set to 1, that is, cf = 1; otherwise, cf = 0.
(2) Parity mark (PF): 8086/8088 the CPU uses odd parity check. After the operation command is executed, when the 8-bit low computation result contains an even number of digits, this flag is set to 1; otherwise, it is set to 0. It is also called an even flag.
(3) Secondary carry flag (AF): After the operation command is executed. When two numbers are added (subtracted), when D3 is directed to D4, this flag is set to 1; otherwise, it is set to 0.
(4) All zero sign (ZF): after an operation command is executed, each bit in the result is zero. This flag is set to 1.
(5) symbol mark (SF): when calculating the number of symbols, if the highest bit of the calculation result is 1, the result is negative, and the SF bit is set to 1, otherwise the SF bit is set to 0. SF is also known as a negative flag.
(6) overflow sign (of): after an operation command is executed, the result value overflows. This flag is set to 1; otherwise, it is set to 0.
(7) direction sign (DF): used for string command operations. When df = 0, string processing is performed from the low address to the high address. When df = 1, from the high address to the low address.
(8) interrupt allowable sign (IF): used to control and shield hardware interruptions. When if = 1, The 8086 microprocessor can accept external interruption requests that can be blocked from the chip and enable interruption. If = 0, external interruption requests are blocked and disconnected, it is also called blocked.
(9) trap sign (TF): used to control single-step interruptions. When TF = 1, the program is executed in one step. That is, each execution of a command in 8086 generates a single-step interrupt in the processor. One-step instruction execution allows programmers to track the instruction execution process and debug the product sequence.
4. Operation Control Circuit

The operating control circuit is the core of the 8086 microprocessor. It first decodes a command sent from the command queue, then, the required control signals are generated based on the functions of different commands to control the operations of various functional components.

 

Biu components: 

1. segment register group (CS, DS, SS, ES)

CS: the segment register that stores the segment address of the program to be executed.

DS: data segment register, which stores the segment address of the operands used by the currently executed program.

SS: Stack segment register, which stores the segment address of the stack used by the currently executed program.

ES: append segment register, which stores the segment address of the operands currently used by the program to be executed.

The content of DS, SS, and ES registers can be set by the program, while the content of CS registers cannot be set by the program.

2. Instruction Pointer register (IP)

It is mainly used to store the offset of the next instruction to be executed and form the physical address of the next instruction in combination with Cs.

3. Address Divider

It is used to calculate physical addresses. The formation of physical addresses:

Physical address = Segment Base Address × 10 h + offset

The 8086 Microprocessor has 20 address buses and can address 1 MB of memory space. Because the 8086 microprocessor is a 16-bit structure and the segment registers are all 16-bit, the 16-bit registers cannot store 20-bit addresses. To solve this problem, 8086 sets a 20-bit Address Calculator. It first shifts the 16-bit segment address four places left, then, a 20-bit physical address is formed by adding the 16-bit offset address:

 

 

Figure 3 physical address Formation

For example, when an instruction is obtained, the code segment register CS is automatically selected, and the 16-bit offset provided by the instruction pointer register (IP) is added, after calculation, obtain the 20-bit physical address of the command to be obtained.

4. command queue Buffer

It is a 6B first-in-first-out buffer. 8086 the microprocessor has the command prefetch function. When the Execution Component (EU) transfers data without using the bus interface component and the off-chip component, the bus interface component can read the command from the memory to fill the command queue buffer. 8088 the instruction queue buffer of the microprocessor is only 4B in depth.

 

5. Bus Interface Control Logic

This part of the circuit is the interface between the processor and the external bus. It first sends the formed 20-bit address code out of the chip through the address line, and then transmits the operand or command code through the data bus. The operands are sent to the related registers or from the related registers to the off-chip devices, and the instruction code is read from the off-chip memory to the instruction queue for decoding.

 

Ii. Memory Management of 8086/8088 Microprocessor

 

8088/8086 the CPU has 20 address buses and can address 1 MB of memory space. Because the 8086 microprocessor is a 16-bit structure and the segment registers are all 16-bit, the 16-bit registers cannot store 20-bit addresses. For how to solve this problem, please refer to the introduction of the address divider above.

As mentioned above, the 8086 microprocessor is a 16-bit structure with 16-bit segments and registers, so the maximum addressing range is 64 K. 8086/8088 divide the primary storage space of 1 MB into several segments, each of which consists of continuous byte units. The maximum length is 64 K (that is, 65536 ). Each segment can be used as a logic unit for independent addressing. The code and data in a segment can be stored in any unit in the segment. The starting address of each segment must be divisible by 16, that is, the minimum 4 bits in the base address of the 20 bits must be "0 ". The high 16-bit binary code of the first segment address is the segment number (base segment address) or segment address. The segment address is stored in the segment registers CS, DS, SS, and es, set different values for the segment register to direct the segment register of the microprocessor to different segments in the memory. [2]

The segments set in the program are called logical segments. The size of each logical segment is determined based on actual needs. The maximum size is 64 KB. The actual application time can be smaller than 64 KB. the unused space can be further defined as the space of other segments, so overlapping segments may occur. Each logical segment can be adjacent, separated, partially overlapped, and completely overlapped. [3]

In the 8086/8088 microprocessor, three terms related to memory addresses are described: physical address, offset address, and logical address.

(1) physical address: it is a 20-bit address code sent from the 8086/8088 chip address. It is used to participate in the address decoding of the memory, and a specific storage unit accessed by the final read/write.

(2) offset address: the difference between a storage unit and the first address of the segment, using 16-bit binary code.

(3) Logical Address: represents a memory address in a program:

Logical Address = segment address: Offset address

 

References:

[1] http://www.sgrtvu.net.cn/jx_data/lg_data/czs/wjjk/chapter2_2a.htm

[2] http://www.hljrtvu.com/xbwz/lg/myweb/d2/2.2.htm

[3] http://hi.baidu.com/hyap/blog/item/4fbdeafe3f9c2d375d60086c.html