0.12 Complete analysis of a little discrepancy, the following is the positive solution:
Turn from:
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In addition this series of articles looks good, after the collection slowly look:
The Art of Assembly Language programming
Http://cs.smith.edu/~thiebaut/ArtOfAssembly/artofasm.html
17.4 Hardware InterruptsHardware interrupts are the form most engineers (as opposed to PC programmers) associate with the term interrupt. We'll adopt this same strategy Henceforthand'll use the non-modified term ' interrupt ' to mean a hardwareinterrupt.
On the PC, interrupts come from many different sources. The primary sourcesof interrupts, however, are the PCs timer chip, keyboard, serial ports,parallel, ports, disk drives, CMO S real-time clock, mouse, sound cards, andother peripheral. These are devices connect to a Intel 8259A programmableinterrupt controller (PIC) that prioritizes the interrupts and Interfa Ceswith the 80x86 CPU. The 8259A chip adds considerable complexity to the softwarethat processes-interrupts, so it makes perfect to sense The Picfirst, before trying to describe how the interrupt service routines Haveto with it. Afterwards, this section would briefly describe each deviceand the conditions under the IT which the CPU. This text would fullydescribe many of the devices in later chapters and so this chapter would notgo into a lot of detail PT when discussing the timer interrupt.
17.4.1 the 8259A programmable Interrupt Controller (PIC) The 8259A (8259 [6] or PIC, hereafter) Programmableinterrupt controller chip accepts interrupts from up to eight different Devices. If any one of the devices requests service, the 8259 'll togglean interrupt output line (connected to the CPU) and pass a Programmableinterrupt vector to the CPU. Can cascade the device to support up to64 devices by connecting nine 8259s together:eight of the devices witheight in Puts each whose outputs become the eight inputs of the ninth. A typical PC uses two of this devices to provide interrupt inputs (Sevenon the master PIC with the eight input coming From the slave PIC to processits eight inputs) [7]. The sections following Thisone'll describe the devices connected to each of those inputs, for NOWWE would concentrate on What the 8259 does with those inputs. Nevertheless,for the sake of discussion, the following table lists the interrupt the PC:
8259 Programmable Interrupt Controller Inputs
| Input on 8259 |
80x86 INT |
Device |
| IRQ 0 |
8 |
Timer Chip |
| IRQ 1 |
9 |
Keyboard |
| IRQ 2 |
0Ah |
Cascade for Controller2 (IRQ 8-15) |
| IRQ 3 |
0Bh |
Serial Port 2 |
| IRQ 4 |
0Ch |
Serialport 1 |
| IRQ 5 |
0Dh |
Parallel Port 2 in, reserved in PS/2 systems |
| IRQ 6 |
0Eh |
Diskette Drive |
| IRQ 7 |
0Fh |
Parallel Port1 |
| IRQ 8/0 |
80G |
Real-time clock |
| IRQ 9/1 |
71h |
Cgavertical Retrace (and other IRQ 2 devices) |
| IRQ 10/2 |
72h |
Reserved |
| IRQ 11/3 |
73h |
Reserved |
| IRQ 12/4 |
74h |
Reserved in At,auxiliary device on PS/2 systems |
| IRQ 13/5 |
85G |
FPU Interrupt |
| IRQ 14/6 |
76h |
Hard disk Controller |
| IRQ 15/7 |
77h |
Reserved |
The 8259 PIC is a very complex chip to program. Fortunately, all of thehard stuff has already been do for your by the BIOS when the system boots. We are not discuss you to initialize the 8259 in this text because thatinformation are only useful to those writing ing systems like linux,windows, or OS/2. If you are want your interrupt service routines to run Correctlyunder DOS or no other OS, your must not reinitialize the PIC.
The PICs interface to the system through four I/O locations:ports 20h/0a0hand 21h/0a1h. The "the" the "in" is the "Masterpic" (IRQ 0-7), the second address in each pair corresponds to T He slavepic (IRQ 8-15). Port 20h/0a0h is a read/write location to which for you writepic commands and read PIC status, we'll refer to this as the CO Mmand registeror the status register. The command register is write only and the status Registeris read only. They just happen to share the same I/O location. The Read/writelines on the PIC determine which register the CPU accesses. Port 21h/0a1his A read/write location that contains the interrupt mask register and we willrefer to this as the Mask register . Choose the appropriate address Dependingupon which interrupt and controller to use.
The Interrupt mask register is a eight bit register that lets your individuallyenable and disable interrupts from devices On the system. This is Similarto the "CLI" and STI instructions,but on a device by device basis. Writing a zero to the corresponding bitenables that device ' s interrupts. Writing a one disables interrupts fromthe affected device. This is non-intuitive. The figure below providesthe layout of the interrupt register.
When changing bits in the mask register, it are important that you notsimply load Al with a value and output it directly to The Maskregister port. Instead, you should read the mask register and then logicallyor in or with the bits you want to change;finally, can Write the output back to the mask register. The Followingcode sequence enables com1:interrupts without affecting any others:
in Al, 21h ; Read existing bits. and Al, 0efh ; Turn on IRQ 4 (COM1).
Out 21h, Al ; Write result back to PIC.
The command register provides lots of options, but there are only threecommands your would want to execute on this chip tha T are compatible withthe BIOS ' initialization of the 8259:sending an ' of interrupt Commandand sending one of two read Status register Commands.
One a specific interrupt occurs, the 8259 masks all further interrupts Fromthat device until are receives an end of Interru PT signal from the Interruptservice routine. On PCs running DOS, your accomplish this by writing Thevalue 20h to the command register. The following code does this:
mov al, 20h
out 20h, Al ; Port 0a0h if IRQ 8-15.
You are must send exactly one end of interrupt command to the PIC for each interruptyou service. If you don't send the end of the ' Interrupt command, the PIC Willnot honor any further interrupts from that device; If you send two or moreend of interrupt commands, there is the possibility this you'll accidentallyacknowledge a new int Errupt that May is pending and you are lose that interrupt.
For some interrupt service routines you write, your ISR won't be theonly ISR this interrupt invokes. For example, the PC's BIOS Providesan ISR for the timer interrupt that maintains the time of the. If you are patchinto the timer interrupt, you'll need to call the PC BIOS ' timer ISR sothe system can properly maintain the Time of day and handle the other timingrelated chores (for "chaining interruptservice routines" on page 1010). However, the BIOS ' timer ISR outputsthe end of interrupt command. Therefore, should not output the "End ofinterrupt command yourself, otherwise the BIOS would output a second endof Rupt command and you lose a interrupt in the process.
The other two commands your can send the 8259 let you select whether to readthe in-service register (ISR) or the interrupt Request register (IRR). Thein-service register contains set bits for each active ISR (because the 8259allows prioritized interrupts, it is quite p Ossible that one ISR has beeninterrupted by a higher priority ISR). The interrupt request register Containsset bits in corresponding positions for interrupts then have not yet beenserviced ( Probably because they are a lower priority the interrupt than theinterrupt currently being by the system). To read the In-serviceregister, you would execute the following statements:
; Read the In-service register in PIC #1 (at I/O address 20h)
mov -AL, 0bh out 20h, AL in
al, 20h
To read the interrupt request register, your would use the following code:
; Read the interrupt request register in PIC #1 (at I/O address 20h)
mov -AL, 0ah out
20h, AL in al, 10K
Writing the "other values" to "command port may cause your system to malfunction.
17.4.2 the Timer Interrupt (INT 8)The PC ' s motherboard contains an 8254 compatible timer chip. This chipcontains three timer channels, one of which generates interrupts every 55msec (approximately). This is about once every 1/18.2 seconds. You are Willoften hear this interrupt referred to as the eighteenth second. We'll simply call it the timer interrupt.
The timer interrupt vector is probably the most commonly patched interruptin the system. It turns out there are two timer interrupt vectors in Thesystem. Int 8 is the hardware vector associated with the timer interrupt (since it comes into IRQ 0 on the PIC). Generally, you should not patchthis interrupt if you are want to write a timer ISR. Instead, you should patchthe second timer interrupt, interrupt 1ch. The BIOS ' timer interrupt handler (int 8) executes an int 1ch instruction before it returns. This gives a user patched routine access to the timer interrupt. Unlessyou are willing to duplicate the BIOS and DOS timer code, you should nevercompletely replace the existing timer ISR With one of the your own, your shouldalways ensure that BIOS and DOS ISRs execute in addition to your ISR. patching into the int 1ch vector are the easiest way to doing this.
Even replacing the int 1ch vector with a pointer to your an ISR is very dangerous. The timer interrupt Service routine is the one most commonly patched byvarious resident. By simply writing, your ISR intothe timer interrupt vector, your may disable such resident and programs Your system to malfunction. To solve this problem, you are need to create aninterrupt chain. For more details, "Chaininginterrupt Service Routines" on page 1010.
By default the timer interrupt are always enabled on the interrupt controllerchip. Indeed, disabling this interrupt could cause your system to crash orotherwise. At the very least, your system won't maintain thecorrect time if you disable the timer interrupt.
17.4.3 the keyboard Interrupt (INT 9)The keyboard microcontroller on the PC ' s motherboard generates two Interruptson all keystroke-one when you press a key And one when you release it. This is in IRQ 1 on the master PIC. The BIOS responds to this interruptby reading the keyboard's scan code, converting this to a ASCII Character,and storing The scan and ASCII codes away in the system type ahead buffer.
By default, this interrupt is always enabled. If You are disable this interrupt,the system'll is able to respond to any keystrokes, including Ctrl-alt-del. Therefore, your programs should always reenable this interrupt if they everdisable it.
17.4.4 the serial Port interrupts (int 0Bh and int 0Ch)The PC uses two interrupts, IRQ 3 and IRQ 4, to support interrupt drivenserial. The 8250 (or compatible) serial communications controllerchip (SCC) generates an interrupt in one of four situations:a ch Aracterarriving over the serial line, the SCC finishes the transmission of a characterand was requesting another, an error Occurs, or a status change occurs. THESCC activates the same interrupt line (IRQ 3 or 4) to all four interruptsources. The interrupt Service routine is responsible to determining theexact nature of the interrupt by interrogating the SCC.
By default, the system disables IRQ 3 and IRQ 4. If You are install a SERIALISR, you'll need to clear the interrupt mask bit in the 8259 PIC Beforeit'll respond to Interru Pts from the SCC. Furthermore, the SCC designincludes its own interrupt mask. You'll need to enable the interrupt Maskson the SCC chip as. For more information on the SCC, the Appropriatechapter.
17.4.5 the Parallel Port interrupts (int 0Dh and int 0Fh)The parallel port interrupts are an enigma. IBM designed the Originalsystem to allow two parallel port interrupts and then promptly Designeda printer interface card t Hat didn ' t support the use of interrupts. As Aresult, almost no DOS based software today uses the parallel port interrupts (IRQ 5 and IRQ 7). Indeed, on the PS/2 systems IBM reserved IRQ5 which theyformerly used for LPT2:.
However, these are interrupts have not gone to waste. Many devices which IBM ' sengineers couldn ' t even conceive when designing the ' the ' the ' the ' of have . Examples include SCSI cards and sound cards. Manydevices today include "interrupt jumpers" so let you SELECTIRQ 5 or IRQ 7 when installing the device.
Since IRQ 5 and IRQ 7 find such little use as parallel port interrupts,we'll effectively ignore the "parallel port Inter Rupts "in Thistext.
17.4.6 the diskette and Hard Drive interrupts (int 0Eh and int 76h)The floppy and hard disk drives generate interrupts at the Completionof a disk operation. This is a very useful feature for multitasking systemslike OS/2, Linux, or Windows. While the "disk is reading" or writing data,the CPU can go to execute instructions for another process. When the disk is finishesthe read or write operation, it interrupts the CPU so it can resume theoriginal task.
While managing the disk drives would was a interesting topic to cover-text, this book is inthis long already. Therefore, this text would avoiddiscussing the disk drive interrupts (IRQ 6 and IRQ) in the Interestof saving some spaces . There are many texts that cover-level disk I/oin assembly, and the language for details.
By default, the floppy and hard disk interrupts are always enabled. Youshould not change this status if you are intend to use the disk drives on Yoursystem.
17.4.7 The Real-time Clock Interrupt (INT 70h)Pc/at and later machines included a CMOS real-time clock. This deviceis capable of the generating timer interrupts in multiples of 976 msec (let's call it 1 msec). By default, the real-time clock interrupt is disabled. You are should only to enable this interrupt if you are have an int 70h ISR installed.
17.4.8 the FPU Interrupt (INT 75h)The 80x87 FPU generates a interrupt whenever a floating point exceptionoccurs. On CPUs with built-in FPUs (80486DX and better) there are a bit inone of the control register for you can set to simulate a VEC Tored interrupt. BIOS generally initializes such bits for compatibility with existing systems.
By default, BIOS disables the FPU interrupt. Most programs that use THEFPU explicitly test the FPU's status register to determine if a error occurs. If you are want to allow FPU interrupts, you are must enable the interrupts on the8259 and on the 80x87 FPU.
17.4.9 nonmaskable interrupts (INT 2)The 80x86 chips actually provide two interrupt input pins. The Firstis the maskable interrupt. This is the pin to which the 8259 PIC connects. This interrupt are maskable because you can enable or disable it with the CLI and STI instructions. The nonmaskable interrupt,as its name implies, cannot is disabled under software control. Generally,pcs use this interrupt to signal a memory parity error although the use this certainsystems for the other pur Poses as. Many older PC Systemsconnect the FPU to this interrupt.
This interrupt cannot being masked, so it is always enabled by default.
17.4.10 Other interruptsAs mentioned in the "the" 8259 PIC, there are several interruptsreserved by IBM. Many systems use the reserved interrupts for the Mouseor for other purposes. Since such interrupts are inherently system dependent,we'll not describe them.
[6] The original 8259 is designed for Intel ' s8080 system. The 8259A provided support for the 80x86 and some other features. Since almost no one uses 8259 chips anymore, this text would use the Genericterm 8259. [7] The original IBM PC and Pc/xtmachines only supported eight interrupts via one 8259 chip. IBM, and Virtuallyall clone manufacturers, added the second PIC in Pc/at and later.
