8.ARM registers a detailed explanation of the simple classification of ARM registers: Figure 1-1:

8.ARM Register Detailed explanation

Simple classification of ARM registers: Figure 1-1:

Figure 1-1

There are 37 32-bit registers in the arm microprocessor, including 31 universal registers and 6 status registers. However, these registers cannot be accessed at the same time, and there are different types of registers that can be accessed in seven modes. However, the Universal Register R14--R0, the program counter PC, and a status register CPSR are all accessible.

The specific situation is shown in 1-2:

Figure 1-2

Register Classification:

???? 1, non-grouped universal registers:

The R0-R7 is a non-grouping register. The so-called non-grouping is to access the same physical register address in any of the seven modes. Is that the non-grouping register has no privileged mode, and either mode can use an ungrouped register.

???? 2. Packet Register R8--R12:

Fiq Mode Group Register R8--r12.

Packet registers other than Fiq R8-----R12

???? 3. Packet register R13, R14:

The register R13 is typically used as a stack pointer sp.

Register R14 is used as the subroutine link register (link register LR), also known as LR, to the return address of the function.

???? 4. Program Counter:

Register R15 is used as a program counter, also known as a PC. The value is equal to the address +8 of the currently executing instruction (because there is a more decoding phase between the fetch and the execution). The PC always points to the post two instruction address that is running, which is the address +8 of the current execution instruction.

???? 5. Status Register:

Figure 1-3:

Figure 1-3

The program status register CPSR can be accessed by arm in all operating modes. The CPSR contains conditional flag bits, interrupt control bits, current processor mode, and other state and control information. CPSR has a corresponding physical register in each of the exception modes----The program state holds the register SPSR. When an exception occurs, SPSR is used to hold the value of CPSR so that the exception is returned and the state of the operation when the exception occurs is resumed.

CPSR Status register: Figure 1-4:

Figure 1-4

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Figure 1-5:

Figure 1-5

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Arm Framework Documentation

31 Universal Registers, 6 status registers (one cpsr,5 spsr).

The general 31 registers are divided into three classes: R0~R7,R8~R14,PC program counter (R15).

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R13 often do stack pointers.

R14 saves the return address of the calling child function, and the return address of the interrupt.

For program counters, PC pointers.

Cpsr

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Explain:

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8.ARM registers a detailed explanation of the simple classification of ARM registers: Figure 1-1: