(9) msp430f5529 timer timer_a

msp430f5529There are two categories of total4timer, timer_a timer 3 and timer_b timer 1 , according to each register with a capture /the number of comparators is named timer0_a(with 5 capture comparators),timer1_a(3 ),timer2_a( 3 ),timer0_b(7 ).

In this chapter, we talk about timer timer0_a. ( A classes are the same)

Note: All registers mentioned below are listed in the TA Back Insert 0 or 1 or 2 they say, respectively . timer0_a , timer1_a , timer2_a (I omitted the numbers here)

6.1 Brief Introduction

Timer A is a 16-bit timing (plus minus) counter that is combined with a capture/compare register . Timer a supports multiple capture/compare, PWM output and internal timing with extended interrupt capability, which can be generated by a timer overflow or by a capture/compare register .

Features Introduction:

0 Asynchronous 16-bit timing/counter with four operating modes

0 Self-timer source selectable configuration

0 up to 5 configurable capture/comparison registers (CCR)

0 Configurable PWM outputs

0 asynchronous input and output latches

0 Interrupt vector Register for fast response to all timer_a interrupts      

6.2 TA ( timer_a ) Several basic operation settings (including register introduction and setting)

Disclaimer: All registers also support word and byte operations, don't forget what this means

All registers are initialized to 0x0000

6.2.1 TA Control Register tactl (most commonly used most basic )

              &NBSP Explain again for example: ta0ctl , ta1ctl , ta2ctl The represents each 3 different Timer a control register ,  rw-(0) means that the default reads and writes are 0  

tasselx : Clock source Selection. Try not to select the tassel0-taclk external clock source, because if the taclk and CPU clocks are out of sync, it's easy to get a problem. (ta0clk connect P1.0 pin)

xx taclk ACLK Ten SMCLK ~TACLK

IDx : first-time crossover control. id0-1 Division,id1-2 frequency Division,id2-4 crossover,id3-8 crossover

MC: Operating mode control. (It is recommended to stop the timer (interrupt enable, interrupt flag,taclr exception) before modifying the timer operation mode to avoid unknown misoperation.) ）

  00  Stop mode: Timer stop     01  Add mode:   timer count to taccr0    10  continuous mode, timer count to 0fffh    taccr0 then counts down to 0000H 

　　 TACLR : Timer Clear 0 bits . The position bit resets the TA Register, the clock divider, and the counting direction. taclr bit will automatically reset and reset 0

Taie　　 : timer interrupt Enable 0 : Interrupt Disable 1 : interrupt Allow

TAIFG　　 : interrupt Flag bit 0 : no interruption occurs 1: There is an interrupt pending

6.2.2 Count Value Store register TAR

① Obviously, the maximum storage count value is 0xFFFFh;

②(similar to the SCM) can be used to store an initial value, and then choose a continuous mode. In this way, it is constantly filled and then manually filled to achieve the precise timing effect;

③ Default is 0, and the register can be directly assigned to the value;

6.2.3 Extended Register TAEX0

Very simply, this register is to control the clock source two times (see structure chart).

The Lower 3 of the Register is defined as taidex:000-111 , respectively, represents the 1-8 divider

6.2.4 capture / Compare registers TACCR0-TACCR4( Total of 5 )

comparison mode, used to set the end value of the count;

Capture mode is used to store the captured TAR values in taccrx .

6.3 MC detailed explanations of the four operating modes controlled

6.3.1 mc=0 Stop mode

This is the system default mode, the timer counter is forbidden to work.

6.3.2 mc=1 A few words: (The red mark is very important)

① This mode is strictly forbidden to count from the beginning of 0xFFFF ;

② Note from 0 to TACCR0, actually recorded the number of taccr0+1 ;

After the ③ counts to TACCR0 , it returns to 0 to start counting again;

④ If the value of TAR is greater than TACCR0, it will be counted immediately starting at 0 ;

⑤ When the timer is counted to the value of TACCR0 , the interrupt flag CCIFG bit (which is then referred to) is placed. When the timer is returned by TACCR0 0 , theTAIFG interrupt flag is placed;

⑥ modifies the TACCR0when the timer is running, and if the new period value is greater than or equal to the old period value, or is greater than the current timer count value, then the timer starts to perform a new cycle count immediately. If the new period is less than the current count, then the timer returns to 0. However, there will be an extra count before returning to 0 .

6.3.3 mc=2 Continuous Mode

in continuous mode, the timer is repeatedly counted to 0FFFFHand then re-counted from 0 (unless the initial value of each reload counts). When the timer is from 0FFFFH to 0 , theTAIFG interrupt flag is placed.

Application: Use the capture / comparator to generate the required time interval in continuous mode. The principle is: The count is always in progress, the trap TACCRX has the first count end value, each time the capture device counts to TACCRX , will produce the interrupt flag, we can write a calculated next count end value in the Interrupt service function, With this infinite computation and interruption, the trap produces a stable time interval sequence. (Actually, it doesn't matter if you don't understand.) Even if you understand, it is not good, because it is cumbersome to calculate and not good to use.

6.3.4 mc=3 Increment/Decrement mode (commonly used to generate PWM Wave)

① This mode, the counting direction is fixed, that is, to let the timer stop and then restart the timer, it will follow the stop count direction and value start counting. If you do not want this, you need to place the taclr to clear the direction. The taclr bit also clears the TAR value and the timer's clock divider.

② This mode with the following position:

③ When the timer is running, change the value of TACCR0 , if it is in the case of subtraction, the timer will continue to reduce to 0, the new period is reduced to start after 0. if it is in the increment count state, the new period is greater than or equal to the original period, or greater than the current count value, the timer will be added to the new period, if the new period is less than the original period, the timer starts to decrement the count, but before the timer starts to decrement the count will be counted.

Article excerpt from: http://blog.lehu.shu.edu.cn/879836630/A449667.html

(9) msp430f5529 timer timer_a