9.2 Structure of the interrupt vector table

Computer composition 9 interrupts and Exception 9.2 interrupt vector table structure

I now know that when an operation is encountered in an abnormal situation, the first line of the first page to start writing the instructions of these operations, began to execute. Start down and this will solve the problem. But the problem is that this operation solves the problem that the result of my calculation cannot be filled in the blanks. But what should I do when I have a new problem? We may also encounter a lot of other problems. At this point, the manufacturer of the handbook actually needs to make some improvements.

The first page of the manual cannot be written in a single resolution scenario. He's going to draw a form, 12345 in this form, and fill in a different situation. We encountered the unknown operation symbol, please see the first page of the second article; If this place has a bug, then you can not see the figure, please see the sixth of the first page. So that we can solve the different situation.

Let's review UNIVAC's approach to exception handling first. When the arithmetic operation overflows, UNIVAC turns to address 0 to remove the instruction. Two repair instructions will be executed there. This approach is already very flexible. But there are still some areas that deserve improvement. For example, in memory, if only two instructions are reserved for repair instructions starting at address 0. If you later want to change the way the repair, you need to add a few more instructions, the space reserved here is probably not enough. In addition, when the number of anomalies that need to be handled becomes more numerous, it is necessary to perform different exception handling instructions depending on the exception condition. If you can only turn to address 0 if you encounter an exception, there is no way to handle many different exceptions. Therefore, improvements need to be made in both areas.

Then take a look at what happened to the 8086?

8086 is a 16-bit CPU. It has four 16-bit universal registers and 16 data cables to the outside. But its address line to be more, a total of 20. This addressable memory space is 2 of the 20 square, which is a trillion byte.

Since its internal registers and operators are 16-bit wide, to generate a 20-bit wide address, you have to use a certain conversion method. 8086 uses the method of paragraph plus offset .

Then for this trillion of space is not all can be used arbitrarily, there are two areas reserved for special purposes. In this 1M byte memory space, the lowest 1K bytes are reserved as interrupt vector table extents, and the highest 16 bytes are reserved for the initialization program area.

We illustrate this with an illustration, where a color-filled block is used to represent this megabyte of memory. After the 8086CPU reset, it sends the address of the first fetch instruction to four f a 0 (ffff0h). This address is the highest 16 bytes of this place in this megabytes of memory space. This area is actually very small, with only a few instructions to put in. What is usually put here is an unconditional transfer instruction that moves to another place in the memory space. In that place are stored the following system procedures.

After the CPU reset, why not start from the full 0 (00000H) address? That would not seem more natural. That's because the address space starting from 0 is already occupied. This 1K (0000H~003FFH) byte is used as the interrupt vector table area, which holds a total of 256 interrupt vectors, with each interrupt vector accounting for four bytes. This is exactly 1K (256*4=\ (2^{10}=1k\)) bytes. In addition to these two dedicated areas, other areas can be used to store general program directives and data. In this area (0000H~003FFH), there are programs that are used for interrupt processing, which are called Interrupt service programs. The starting address of the program code is called the entry address of the interrupt service program.

This is the definition of the interrupt vector.

Today's CPUs are generally able to handle many different types of interrupts.

Each interrupt type corresponds to an interrupt vector, which is 4 bytes in total. Of these four bytes, the first two bytes (06H and 30H) are used to hold the Interrupt Service entry offset, and is low-byte (06H) before, High-byte (30H) behind. Therefore, for this interrupt vector, the two bytes (06H and 30H) are stored in the instruction pointer Register (IP) , and the previous byte (06H) is the low byte in the register, and the latter byte (30H) is the high byte in the register. Then the second two bytes (00H and 40H) in the interrupt vector correspond to the subgrade value of the Interrupt Service entry address, which is used to store the code segment Register , which is the CS register. Then again, the previous byte (00H) corresponds to the low byte in the register, and the subsequent byte (40H) corresponds to the high byte in the register. In the 8086 or later X86 processor real mode, you need to use CS and IP this pair of registers to specify a memory address.

The way this address is generated is called Segment plus offset. The CS register is a segment register, which is 16 bits. The IP register just now corresponds to the offset, which is also a 16-bit. These two 16-bit addresses constitute a logical address. The usual representation is to separate the two 16-digit numbers (CS:IP) with a colon. That is, when the CPU generates the address, the number of the segment Register (CS) is shifted to the left by 4 bits, followed by an offset, so that the junction of the addition operation is the physical address of the 20-bit. This is how the logical address generates the physical address. In fact, the subgrade value is multiplied by 16 plus the offset, and for the binary, left four is the equivalent of multiplying by 16 (the binary left shift four bits is equivalent to the hexadecimal left one bit).

That way, each interrupt vector consists of a two-segment base value and an offset address of two vectors. Since each medium break vector occupies four bytes, there are 256 interrupt vectors in the entire interrupt vector table, named No. 0, 1th, and No. 255 interrupts. This interrupt vector table is initialized when it is started in the system. Suppose the initial value of the number 1th vector is such that when the CPU receives an interrupt, 1th is interrupted if it is found. Because each interrupt vector is placed in a fixed address, the CPU does not need to execute instructions directly through the hardware circuit settings, can issue memory access to read the four bytes of content. The high two bytes are then sent to the CS register, and a low of two bytes are sent to the IP register.

For 8086来, the functions of both registers (CS and IP) are equivalent to the PC registers we mentioned earlier when we introduced the internal structure of the processor. So, once the value of these two registers changes, the next cycle CPU will start to remove an instruction from this new address (CS:IP), according to the calculation method of the segment plus offset, the CPU sends the address is 43006. Therefore, in the case of a 1th interrupt, the CPU will go to the 43006 address to begin executing the program. Of course, there is a need to store the service program for interrupt # 1th here (in memory) beforehand.

Similarly, we will put the service program of interrupt No. 0 in another place of memory, and then break the starting address of the number No. 0 Interrupt program into the segment base value and offset address, stored in the location of the No. 0 interrupt vector. When the CPU encounters an interrupt, if it is found to be No. 0 interrupt, then the No. 0 interrupt vector corresponding to the contents of the content, respectively, into the CS and IP register. The CPU is then removed from the start address of the No. 0 Interrupt service program to execute the instruction.

We note that the sequence of storage in which these interrupt services are stored is not required. Do not need to follow the order of the break type, first put the No. 0 Interrupt service program, and then put the number 1th Interrupt service program, but can be placed at will. You just need to store its starting address in the corresponding position on the interrupt vector table. This is more flexible than the UNIVAC way, an interrupt service program can be long and short, do not worry about the 0-based address in the end to reserve the amount of space to be enough, and the location of the interrupt service program if the change, there is no relationship, do not need to modify the CPU hardware design, Instead, you just need to modify the interrupt vector in the interrupt vector table. In this way, only the interrupt vector table is initialized and the corresponding interrupt service program is prepared in the memory, and the CPU can automatically jump to the corresponding interrupt service program for processing when the interrupt is encountered.

For the related calculations of interrupt vectors, let's look at a few simple exercises.

First, if the interrupt type code, also is called the Interrupt class model is 20H. What should be the logical address where the interrupt vector starts? First, we know that the interrupt vector table is starting at address 0, with a total of 256 interrupt vectors stored sequentially, and each interrupt vector occupying four bytes. So, the location where the interrupt vector is stored is the interrupt class model multiplied by 4, and the interrupt address is 0000:0080. If the four-byte content in this interrupt vector is 10H, 20H, 30H, and 40H, what should be the entry address for the Interrupt service program?

According to the situation we have just described. This four-byte unit has a low two bytes corresponding to the IP register, and a high of two bytes corresponds to the CS register. and the lower address of this byte is placed in the lower position of the register. Therefore, the entry address of this interrupt service program should be 4,030:2010. These two exercises are a description of the CPU's work when it encounters an outage. If the CPU now encounters the Interrupt class model is 20H, then the hardware will be multiplied by 4 of the operation, resulting in this logical address (0000:0080). The logical address is then sent to memory, which reads back the contents of these four bytes (10H, 20H, 30H, and 40H). Then, according to the principle that we have just set out the two 16 digits (4,030:2010), and the two 16 digits are stored in the CS and the IP register respectively. This will send the new address to the memory at the next clock cycle to remove an instruction.

Then we'll look at another exercise.

If we are now going to write a new interrupt service for the 17H interrupt, and put the interrupt service in one place of memory, the address is 2340h:7890h.

Now we need to update the interrupt vector table. Now the question is, which four bytes in the Interrupt vector table do we want to update? And what kind of content is it updated? Then we can count it together. Since the interrupt class model is 17H, the address that corresponds to the interrupt vector should be multiplied by 4 (17*4 = 5C (mod 16)). Starting from this address (0000:005c), to the high address grows, altogether 4 bytes. So, the logical address for this four byte is this (the first empty).

What should be the contents of each of the four byte units? Then keep this principle in mind if you look at this logical address (2340:7890h) from right to left. The rightmost byte (90H) is placed at the lowest address, and the leftmost byte (23H) is placed at the highest address. These four bytes are emitted sequentially. Therefore, the address from low to high four bytes content should be 90, 78, 40, and 23 respectively.

The two exercises show the CPU hardware to find the interrupt vector table process, and ready to interrupt the service program to initialize or modify the interrupt vector table process.

For the 8086 interrupt vector table CPU has been fixed using the first five types of interrupts, the specific features we will introduce later. The following 27 interrupts (5~31) are also reserved for subsequent CPU use. In addition to the first 20 interrupts, the next 224 interrupts are given to users who use the CPU to define their own.

We now know that the first page of our manufacturer has given us a table. A total of 256 articles. When we encounter the abnormal situation, we can find the corresponding table item according to the different situation in accordance with the prior agreement. The table item actually refers to a page number. For example, fourth says turn to 12th page, this 12th page turned over, wrote the concrete operation, we should do what thing, the operation is quite complicated, wrote several pages, we all put in a page of paper is not fit. So that's how we're going to deal with exceptional situations right now.

The contents of this table may need to be further expanded as we increase the number of computational tasks. Next, let's look at how it expands.

9.2 Structure of the interrupt vector table