9.3 Development of the interrupt vector table

Computer composition 9 interrupts and exceptions 9.3 interrupt vector table development

Now the maker of the handbook has said that he left a table on the first page, a total of 256 lines. Although not complete now, but behind, with the continuous upgrade, the introduction of new manuals when? will continue to supplement some of the following provisions.

Let us now take a look at the history of this Handbook how it complements this clause.

This is 8086 of the total one trillion address space, where the lowest 1K bytes are fixed to place the interrupt vector table. This interrupt vector table includes 256 interrupt vectors, each of which is 4 bytes (256*4=1k). These 4 bytes point to the entry address of the corresponding interrupt service program.

In 8086CPU, the first 5 types of interrupts have been specified. Type 0 is a division error, and when the division operation goes wrong, the CPU will take the interrupt vector and invoke the corresponding interrupt service program. Type 1 is a single step, type 2 is a non-shielded interrupt, type 3 is a breakpoint interrupt, and type 4 is the interrupt of the arithmetic overflow we mentioned at the very beginning.

From type 5 to type 31 is not defined in 8086, but it shows that these interrupt types are CPU-reserved. With the subsequent enrichment of CPU functionality, these interrupt class models will be used to provide new interrupt services.

So let's take a quick look at what new interrupt types are available to the CPU later.

After 8086, the new interrupt type is continuously added.

For example, type 6, called an undefined opcode. After the CPU has retrieved an instruction encoding from memory, it is found that the encoding is not part of any instruction defined in the current instruction system, and the CPU naturally does not know what to do with the corresponding operation. What should I do if we don't have an agreement at the beginning of this situation? Later, when this type of interrupt is added, the CPU can generate an interrupt of type 6 and invoke the corresponding interrupt service program whenever it encounters an undefined instruction opcode. The Interrupt service program may be typing a line on the screen, saying that an undefined instruction has been encountered, and then stopping the currently running program, or skipping the instruction to continue execution. This depends on how the interrupt service program is written.

Then there are some other types of interrupts added, some of which are marked with an asterisk starting from 386, and two asterisks are starting from 486. There are some types of interrupts that have been processed for exceptions that were not previously handled, and more of the new interrupt types based on the added functionality of the CPU. The new interrupt type will be defined later, as the instruction system body is further upgraded and the CPU is improved.

This is the change in the content of the interrupt vector table, let's take a look at the location where the interrupt vector table is stored.

This is the internal structure of the now more popular PC. If it runs in real mode, it can be thought of as a very fast 8086. Therefore, when the CPU is reset, it also goes to the top 16 byte position in the 1 Gigabit address space to fetch the first instruction, which will be booted to the BIOS chip by the North and South Bridge chipset. The CPU performs the instructions in the BIOS chip, and the basic configuration of each device on the motherboard. One of the tasks is to build the interrupt vector table in the main memory address 0, the so-called build interrupt vector table, also to the lowest 1K bytes in main memory to fill those interrupt vectors. After the interrupt vector table is constructed and the interrupt service program is ready, the CPU can access the interrupt vector table in main memory and call the corresponding interrupt service program.

But we also know that the current CPU is not actually running in real mode, memory is not just a trillion. As a result, the way the CPU accesses memory has also changed.

We use the address of the instruction as an example, in real mode is combined with the code segment Register CS and the instruction pointer of the memory IP . Both registers are 16-bit, and their combination produces a 20-bit address in the form of a segment plus offset. However, starting from 386, the instruction pointer register is extended from 16 bits to 32 bits, the EIP register. Then it has 2 of the 32-bit addressable capacity, which is the 4G byte unit. From 386 onwards, the 32-bit CPU is a 32-bit address line, the addressable range is also 2 32 times. At this time, the width of the instruction Pointer Register (EIP) and the actual range of addresses required are already one by one corresponding. Therefore, in protected mode, although the logical address is written in the form of CS register and EIP Register, but the physical address is produced in a way that is completely different from the real mode.

In protected mode, the segment base is not stored in the CS register, but in memory. So take a look at how the CPU is addressing the memory at this time.

Somewhere in memory, a table is stored, called a descriptor table. This table has a total of 8192 (\ (2^{13}\) ) table entries, each of which consists of 8 (\ (2^3\) ) byte, which is called a descriptor. In this descriptor, the 2nd, 3, 4, and 7th bytes, which are all 4 bytes, are the base address, which corresponds to the content stored in the CS register in real mode. In this descriptor, there is something else besides the base site. For example, paragraph boundaries, which indicate how long this paragraph is; there are several bits in it that specify whether the content of this paragraph is readable, writable, and so on. These descriptors are stored in memory and how can the CPU be accessed? Therefore, the use of CS registers is actually modified in the CPU. We can think about why there's a total of 8,192 descriptors? This is related to the width of the CS register, and the CS register is 16 bits wide. So, it can address a total of 2 of the 16 memory units, which is 64K. And because each descriptor is 8 bytes, 8,192 descriptors are exactly 64K (8192*8=\ (2^{13}\) *\ ( 2^3\) =\ (2^{16}\) =64k). Therefore, it is possible to find so many descriptors with the CS register.

But the address of this descriptor is not 0, so to find the corresponding descriptor, the CPU has to know the starting address of the descriptor. Therefore, in the CPU also need to set up a new register, called GDTR, which is used to save the descriptor table of the starting address. so you have to ask again? Where does the content of this gdtr come from? The actual reason is that the x86 CPU will go into real mode when it is started. In real mode, the descriptor table is filled in somewhere in the memory, and then the starting address of the form is filled into the GDTR register. This (GDTR) is also a memory inside the CPU, but it is not like Ex,edx these registers can be used as data operations, it is a special register, but also can be accessed with specific instructions. Therefore, in the protection mode, each time the CPU to access the memory, the contents of the CS register, plus the contents of the GDTR registers to get an address. Use this address to access the memory, and then take out the descriptor, then the descriptor of the 4 bytes of the base address, and then the instruction pointer to the contents of the EIP is combined to obtain the memory address to access, and then use this address to access the memory, to obtain the desired instruction code.

Since in protected mode, every access to the memory must undergo this process, the Access interrupt vector table is no exception. Moreover, the position of the interrupt vector table has changed.

In protected mode, the interrupt vector table is not placed in the memory area of address 0, but can be placed in memory anywhere. And its name also has some changes, called the Interrupt descriptor table. So now, somewhere in memory, there are 256 descriptors in this interrupt descriptor table, each of which is 8 bytes. Of these 8 bytes, byte 0 and byte 1, and Byte 6, byte 7, are all 32-bit addresses, while Byte 2 and byte 3 are a segment selector. When the CPU is interrupted, the interrupt descriptor is still found according to the interrupt class model, since the starting address of the interrupt descriptor is not 0, so the CPU must first know the starting address of the interrupt descriptor, which is also stored in the CPU of a register, called IDTR is the address register that interrupts the descriptor descriptor. The contents of this register also need to be filled in by the system initialization software after setting up the interrupt descriptor.

Now the CPU needs to multiply the interrupt class model by 8 plus the contents of the IDTR register to get the address of the corresponding interrupt descriptor. After retrieving the descriptor, the 16 bits of the segment selector are stored in the CS register, and the 32 bits corresponding to the address are stored in the EIP register. We note that this action is actually similar to real mode, except that each interrupt vector in real mode is 4 bytes. The two bytes are then placed in the CS register, and two bytes are placed in the IP register. What now? Each interrupt descriptor is 8 bytes, and we also place a portion of it in the CS register, and the other part in the EIP memory device. After the completion of this action, if in real mode, the next cycle can directly start from the new address, and in the protection mode, it is not so simple, we also need to follow the same, with the CS register and GDTR with the register, to the memory to find the corresponding Subgrade value. The corresponding memory address can then be combined with the EIP register. This memory address is the entry address of the interrupt service program that we need to invoke. Until then, the CPU will be from the Interrupt Service program entrance, retrieve instructions, really start the processing of interrupts.

Now we know that this table is constantly being supplemented with new content as the handbook is updated. And later on it was not very good to put the table on the first page, to put it in the other position of the manual, this need to use a different way to mark the exact location of the table, or we encounter abnormal situation can not find it. Of course, this part of the content is not our focus, but simply to explain to you a bit. If you are interested, you can analyze the relevant information in depth.

9.3 Development of the interrupt vector table