A big comb of FPGA Knowledge (ii) VERILOGHDL Grammar Introduction (2)

1, timing logic. Modify the last practice to how the timing logic will be designed.

2,block and unblocking

A, nonblocking is usually used in always with clock.

B, blocking is usually used in a clock-free always.

The blocking used in C,assign

D, in the same block, blocking and nonblocking do not coexist.

3, Behavioral modeling

A,if-else and Case latches.

B, cyclic forever,repeat,while,for,generate

4, commonly used IP. Fifo,ram,rom. (Schematic design and code design)

5, precompiled, System tasks and functions.

6, can be integrated and not integrated.

The writing of 7,TB

8, state machine (two kinds of state machine advantages and disadvantages and comparison. One-piece, two-stage, three-stage state machine)

9,task and function

10, reset. Asynchronous release of synchronous reset

11, design skills. Ping-pong, assembly line.

12, string and convert, cross-clock domain.

A big comb of FPGA Knowledge (ii) VERILOGHDL Grammar Introduction (2)