A decoupling bypass circuit consisting of multiple capacitors, how to lay out the capacitance, the first big after small or small after the big?

For noise-sensitive IC circuits, in order to achieve better filtering results, it is often preferable to use a number of different capacitance parallel capacitors in order to achieve a wider filtering frequency, such as in the IC power input with 1μf, 100nF and 10nF parallel can achieve better filtering effect. That's the problem now, these several different specifications of the capacitance in the PCB layout, how to swing, the power supply path is first through the large capacitance and then into the small capacitor and then into the IC, or first through the small capacitance and then through the large capacitor and then input IC.

We know that in practical applications, capacitance is not only the ideal capacitance C, but also the equivalent series resistance ESR and equivalent series inductance ESL, as shown in the following figure is a simplified model of the actual capacitor:

The use of capacitors in high-speed circuits requires attention to an important characteristic indicator is the self-resonant frequency of the capacitor, the capacitance self-resonant frequency formula is expressed as:

The self-resonant frequency point is to distinguish the capacitor is capacitive or perceptual demarcation point, lower than the resonant frequency capacitance performance is capacitance characteristics, higher than the resonant frequency is capacitance performance inductance characteristics, only in the self-resonant frequency point near the capacitance impedance is low, therefore, the actual decoupling capacitor has a certain operating frequency range, Only in the band near its self-resonant frequency point, the capacitance has a good decoupling, the use of capacitors for power decoupling need to pay special attention to this point.

The characteristic impedance of a capacitor can be expressed as:

It can be seen that the self-resonant point of the large capacitance (1uF) is lower than that of the small capacitance (10nF), and the sensitivity of the parasitic equivalent series inductance to the installed PCB circuit board is smaller than that of the small capacitance.

So, the small capacitance should be as close as possible to the IC's power pin placement, large capacitance position relatively loose some, but should be as close to the IC placement, not far from the IC, beyond its decoupling radius, will lose the decoupling effect.

The above situation applies to the situation where the power plane is not used, for high-speed circuit, the general inner layer will have a complete power and ground plane, then the decoupling capacitor and IC power source pin directly through the hole via the power supply, ground plane can, do not need to connect the wire.