A Fast Ethernet Communication System Platform Based on 12301.6

A Fast Ethernet Communication System Platform Based on 12301.6

[Date: 2008-7-22]

Source: Today's electronics/21ic Author: Hunan Institute of Technology Yi Jie

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Introduction

With the increasing popularity of Internet applications, the degree of information sharing is constantly increasing. The digitalization and network of embedded devices have become an inevitable trend. Currently, mainstream embedded operating systems on the market include TCP/IP network protocol stacks. These commercialized TCP/IP protocol stacks run reliably and provide excellent performance, but the prices are high, reducing the market competitiveness. Therefore, the requirement for developing a proprietary TCP/IP protocol stack becomes increasingly urgent and meaningful.

The goal of this paper is to establish a network communication platform for DSP system to achieve high-speed data transmission between DSP system and other communication devices in the network. Although the DSP of TI Company is selected, the solution proposed in this paper has a great degree of versatility, and also has some reference value for other series of DSP or CPU Systems.

Architecture of TCP/IP protocol stack

The most typical application form of Ethernet is Ethernet + TCP/IP, that is, the underlying transmission network built by Ethernet adopts the network transmission protocol TCP/IP that has become a general standard for data communication, this is the most popular and widely used Ethernet communication method today.

The International Organization for Standardization (ISO) has developed an Open System Interconnection (OSI) Reference Model, which divides the processes required for communication sessions into seven independent functional layers, different from the OSI reference model, the TCP/IP model focuses on data transmission between devices, rather than strict hierarchy.

Usually, the OSI reference model is suitable for theoretical explanation of Internet communication mechanisms, while the TCP/IP model is more suitable for specific software implementation.

System Hardware Design

1. Overall System Structure

The Ethernet communication system in this article is divided into five layers: hardware layer, device driver layer, operating system, network module and user code. The system hardware circuit, including the DSP System and the interface circuit of the Ethernet Control Chip Ax88796, is the physical basis of the system. The Fast Ethernet driver is in the hardware abstraction layer. Although it is software, it is closely integrated with hardware and provides a system call for the operating system to access the Fast Ethernet Control Chip Ax88796 or change its working behavior. The μC/OS-Ⅱ operating system is in the system kernel, which provides the underlying services required by users for unified management of system hardware and software resources by user code. The TCP/IP protocol stack software extends the network communication capability for the μC/OS-Ⅱ operating system. The user code processes specific application details. You can use the API functions provided by the TCP/IP module to develop Ethernet-based communication projects.

2 system hardware Diagram

The system hardware includes the interface circuit of the memory chip of and IS61LV51216, and the interface circuit of the memory chip of and the Fast Ethernet Control Chip Ax88796. The software code of the system is stored in the extended RAM in the debugging phase. After it is run offline, it is used to store transmitted image data. Therefore, it is extended by kb. IS61LV51216 memory chip generated by ISSI. The Ethernet Control Chip Ax88796 is connected to the DSP through the ISA interface. It is connected to the Ethernet network after 16ST8515 through the network isolator. When the power supply voltage of the system fluctuates, the power supply monitoring circuit provides a reset signal to the DSP system so that the system program can be re-initialized and run to avoid unexpected errors.

Figure 1 hardware Diagram

3. DSP system hardware design

① System Power Supply Design
To reduce the chip power consumption, 1.8 V (1.9V @ 150 MHz) kernel voltage is adopted for the V chip, but V is used for GPIO, FLASH, and other modules. This topic selects TI's TPS767D301 Power Supply chip. The chip outputs two-way voltage, one 3.3 V, and the other 1.5 ~ 5.5V adjustable, supports 1A current output. In the system, the DSP chip consumes 230mA of the current in normal operation, the maximum current consumption of the Ethernet interface chip is 120mA, the maximum RAM current consumption is 180mA, and the total power consumption of the system is 530mA. Therefore, the TPS767D301 can meet the system requirements.

② System clock design

There are two schemes for the system clock circuit. One is to use an external clock source, that is, an active crystal oscillator. The other is to use the oscillator driving circuit inside the DSP, which is an external crystal and two capacitors. The active crystal oscillator is characterized by the fact that a regular square wave can be output without the internal oscillator of the chip and the rated voltage. The disadvantage is that the output waveform can only be fixed with two voltage values: low level (0 V) and high (input power supply voltage), and high device costs. An external crystal uses an internal oscillator circuit. The output waveform is a sine wave, and the waveform amplitude is determined by the Controller. There is no voltage matching problem.

The I/O pin of 3.3 V is generally 1.8 V, but the clock input foot is an exception. It can only withstand the input voltage of V/1.9V, the 1.8 V/1.9V active crystal oscillator is rarely sold on the market, so passive crystal oscillator is used.

③ Reset Circuit Design

The system has two chips that need to be reset: DSP chip and Ethernet Control Chip Ax88796. However, the two have different requirements for Reset signals. DSP is a low-level reset, while Ax88796 is a high-level reset. Therefore, TI uses the dedicated reset chip TPS3307. The chip has three functions: power-on reset, manual reset, and power monitoring. Circuit 2.

The power-on Reset Circuit ensures that the system automatically generates a reset signal ms after power-on, so that the DSP enters the normal program entry, and the Ax88796 initializes the internal register. The manual reset function is to press the reset button to generate a reset signal when a program runs or the system needs to be re-initialized and run, so that the DSP enters the normal program portal.

④ System RAM Extension

The kB RAM has been integrated into the kB RAM. For general applications, external RAM is no longer needed. However, in-chip RAM can be accessed at a speed of MIPS. In a processing program with high computing speed requirements, frequently accessed program segments are usually put into internal RAM for operation, this greatly improves the running speed, so the on-chip RAM is extremely valuable. Moreover, this system is a network communication system that will be used for network transmission of a large number of images in the future. Therefore, RAM is also required to store image files.

Figure 2 Reset Circuit

RAM uses IS61LV51216 of ISSI, which has a storage capacity of KB × 16 bits, and a power supply voltage of V. The access speeds include 8ns, 10ns, 12ns, and 15ns. When the CPU runs at MHz, the minimum effective time of the address and data is three clock cycles, that is, 20 NS. Therefore, this memory interface does not need to consider timing design issues.

4 Fast Ethernet hardware interface design

The Ax88796 is internally integrated with a 10/100 Mbit/s adaptive physical layer transceiver and 8 K × 16-bit SRAM, supporting various CPU bus types such as MCS-51 series, 80186 series, ISA and MC68K series. Ax88796 provides 10 Mbit/s and 100 Mbit/s Ethernet control functions based on the IEEE 802.3/IEEE 802.3u LAN standard, and uses the IEEE 802.3u-compatible Media-Independent Interface (MII ). In addition, the Ax88796 provides an optional standard printing interface for connecting to a printing device or for general I/O Ports.

① Ax88796 ISA Interface Design

The Ax88796 has two input pins, CPU [1:0], which are used to set different working modes and connect to different CPU buses. When connecting to, the CPU [1:0] is reduced and set to the ISA bus interface. The address bus SA and the Data Bus SD of Ax88796 are connected to the address/Data Bus of 2017121.6 respectively, and the status of the SAS are controlled through I/O reading and writing the registers of Ax88796, data is exchanged between the remote DMA Guest OS and the internal SRAM of Ax88796. The default base address of Ax88796 is 200 H, so the base address range is H ~ 21FH. The ISA interface of Ax88796 has 10 address lines, SA [].

② Ax88796 Power Supply Design

Ax88796 has various voltage types: VDD, VDDA, VDDPD, and VDDO, which provide power for the digital circuit, analog circuit, phase detection module, and transceiver driver module inside the chip. Although it is the same as the 3.3V voltage, in order to prevent each module from winding through the power cord, each power supply is required to provide independent power supply. Therefore, a power supply isolation and filtering circuit is designed to supply the system's 3.3V power supply voltage, LC filtering is used to divide Ax88796 into four-channel voltages.

System Software Design

1. System Software Structure

In addition to application-layer user programs, the system software can be seen as the Function Extension of the operating system μC/OS-Ⅱ: The Ax88796 driver shields the underlying hardware and extends the network device access capability for the operating system; the TCP/IP software extends the network communication capability for the operating system.
TCP/IP is usually divided into a layer-4 protocol system, each layer is responsible for different functions.

● Interface layer: The Ax88796 driver directly accesses the Ax88796 hardware device and controls the behavior mode of Ax88796.
● Network layer: Processes Group Activities in the network, such as group routing.
● Transport layer: Provides end-to-end communication for applications on two hosts.
● Application Layer: responsible for handling specific application details.

Two key aspects of M Fast Ethernet communication implemented on DSP must be considered:

● How to control how hardware devices send data to Ethernet (or receive data from Ethernet to DSP ).
● How to generate the data to be sent (or how to explain the received data ).
The two are solved by the network device driver and TCP/IP protocol software respectively.
The software part of the system includes three aspects: Fast Ethernet driver, μC/OS-Ⅱ operating system and TCP/IP protocol stack software.

2. Fast Ethernet driver development

① Ax88796 register

Ax88796 registers are mapped to 32 address spaces from the base address 200H to the 21FH address space. Therefore, Ax88796 adopts a paging mechanism, and each register is stored on different register pages.

Correctly Setting the Ax88796 register is the basis for system operation. Below are several important registers:

● CR (command register): used to select the register page to start and stop the NIC.
● ISR (Interrupt Status Register): displays the current status of Ax88796. The CPU reads it to determine the cause of the interruption.
● DCR (Data Control Register): select the byte sequence and DMA byte/word transmission mode.
● Pstart, pstop, bnry, and CPR: these four registers are related to the receiving buffer. Pstart settings start page, pstop settings stop page, the two registers set the first and last of the receiving buffer. Bnry indicates the last buffer page to be removed and CPR indicates the first buffer page to be received.
● Tpsr, tbcr0, and tbcr1: these three registers are related to the sending buffer. Tpsr sets the sending buffer start page. tbcr0 and tbcr1 set the number of sending bytes.
● Rsar0, rsar1, rbcr0, and rbcr1: ax88796 exchange data through remote DMA and the system. Set the start address of remote DMA in the first two registers, and set the number of remote DMA data bytes in the last two registers.

② Receiving process

The process of receiving data frames involves two registers: CPR and bnry. The CPR register points to the start page address to be stored for the new received data frame as the write pointer to the local DMA; The bnry register points to the start page address of the data frame that has not been read, as the read pointer to the remote DMA. When CPR catches up with bnry, it indicates that the receiving buffer is full and subsequent data frames will be discarded. When bnry catches up with CPR, it indicates that the receiving buffer is empty.

③ Sending Process

 

Figure 3 sending Process

The sending process is relatively simple, as shown in process 3.

3 transplantation of embedded multi-task operating system μC/OS-ⅱ

The so-called transplantation means that the nuclear energy in μC/OS-ⅱ runs on a microprocessor or microcontroller. For ease of transplantation, most of the μC/OS-ⅱ code is written in C language, but some processor-related code still needs to be written in C and assembly languages, this is because the Read and Write processor registers can only be implemented through the assembly language. Therefore, to make μC/OS-ⅱ run properly, the processor must meet the following requirements:

● The processor supports interruption and can generate scheduled interruption (usually between 10 and 10 ~ 1 kHz ).
● Enable or disable processor interruptions in C language.
● The processor supports hardware stacks that can hold a certain amount of data.
● The processor reads and stores the stack pointer and other registers into the stack or memory.

The transplantation of μC/OS-Ⅱ mainly includes two aspects:

● A c language function in the OS _CPU_C.C File
● Four assembly language functions in the OS _CPU_A.ASM File
Due to limited space, I will not detail the compilation of these two files here.

4 system structure of TCP/IP protocol stack

① Network interface layer Module

The Network Interface Layer module consists of Ax88796 device drivers, buffer zone management, and interface scheduling. The Network Interface abstraction model is defined to shield the physical details of the network, so that upper-layer software can use the same data structure to act on different physical networks.

② ARP Module

ARP maps the upper-Layer Protocol address (IP address) to the underlying hardware address, this forms a line between upper-layer software that can only use IP addresses and drivers of lower-layer devices that can only use physical addresses. The ARP module processes ARP data packets from the network, updates and maintains the ARP high-speed cache, and provides hardware address binding for sending data packets.

③ ICMP Module

The ICMP protocol is rich in content. The most common features are the send and receive response functions implemented by the ping program on the PC. In this topic, the echo response function is implemented, so that users can use the PC to detect whether the DSP Network is smooth. Other functions are currently reserved for future upgrade.

④ IP Module

The IP module is the central link of the entire protocol stack. It receives input data packets from the network, and also receives output data packets from the upper layer protocol. The IP selects a route for the data packets, you can also send it to a network interface or send it to the local upper-layer protocol software (loopback ).

⑤ TCP Module

TCP provides reliable, traffic-controlled, and end-to-end data transmission for unreliable IP connections. The TCP module contains three key processes: data input, data output, and timeout retransmission. The adaptive re-transmission mechanism is the core component of TCP. It can modify the average round-trip time of the connection.

⑥ UDP Module

UDP provides connectionless communication, which is very simple compared with TCP. Although UDP does not guarantee reliability, it is very efficient.

7. Socket interface module

The socket module is mainly used to encapsulate underlying protocol software, making it easier for users to develop network programs on DSP.

System test example

Internet Explorer (IE) is a web browser embedded in the Windows operating system. Web pages are the most widely used information organization form in this information sharing society. By adding web services to the DSP software, the system can be better integrated into the Internet. Users can directly set the system and view the system feedback data through the IE browser. Open IE and type "192.168.8.66" in the address bar to access the remote data collection page in the pre-existing DSP system.

Conclusion

Tests show that the system fully satisfies all functions of the network communication system. It associates the powerful computing and processing capabilities of DSP with the Internet, making the DSP system no longer an "Information Island ", it can easily share information with other devices on the network and further expand the application prospect of DSP.