A remote user access method for DDN nodes

1 Introduction
As a data communication support network, DDN is mainly used to provide users with high-speed and high-quality data transmission channels and provide bridges for their network interconnection. With the economic development of Jiuquan City, China Telecom's DDN has been expanded to the region, which has led to rapid development of data transmission services in the region, including ICBC's data transmission services.
In order to improve business processing capabilities, Jiuquan Industrial and Commercial Bank strives to quickly and efficiently serve the majority of users. It not only requires the Industrial and Commercial Bank of the city to access DDN, but also requires remote users to access DDN, thus, it realizes the transmission of high-speed data between the local industrial and commercial bank and the Industrial and Commercial Bank across the country. The Industrial and Commercial Bank of Jiuquan Satellite Launch Center is a typical example of remote user access to the DDN node of Jiuquan City. The following describes how remote users can achieve normal data transmission through two-way 64 kbit/s.
2 remote user data transmission circuit
Remote users data transmission route Jiuquan satellite transmission center industrial and commercial bank terminal computer 64 kbit/s data), high-speed digital user loop 264 kbit/s HDSL2), high-speed digital user loop 164 kbit/s HDSL1) the PDH Optical Fiber Transmission System of Jiuquan satellite transmission center consists of N × 64kbit/s Data Board 2, optical fiber transmission channel, Jiuquan PDH Optical Fiber Transmission System N × 64kbit/s data board 1, and Jiuquan DDN2 Node.
It can be seen that the entire data transmission circuit is relatively long, reaching about 300km. This access method is not a pure HDLS device or data terminal device in DDN (directly use the data terminal device provided by DDN to access DDN without adding a separate HDLS device) centralized user reuse devices are suitable for scenarios where user data interfaces require a large amount of data or users already have centralized user devices. centralized user devices can be zero group retransmissions, it can also be a small re-adapter provided by DDN). analog circuits are suitable for the direct access to DDN audio interfaces by telephones, fax machines, and user switches after transmission through analog circuits) and 2 Mbit/s digital circuit in DDN, network devices are configured with G.703 2.048 Mbit/s digital interfaces that comply with ITU-T standards, if the user device can provide the same interface, can access DDN nearby) and other typical access methods, but a relatively complex access method, representative in practical applications.
3 features of devices and interfaces in the remote user data transmission circuit
3.1 Transmission Device
3.1.1 high-speed digital user loop HDSL)
HDSL is a dedicated point-to-point public network access device. It adopts advanced adaptive digital Balancing Technology and echo offset technology, it can eliminate signal interference of transmission lines and echo signals that do not match different wire diameter impedance. It can transmit up to 2.048 Mbit/s digital signals in full duplex on Copper Twisted Pair wires, it can also transmit digital signals below 2 Mbit/s in full duplex on Copper Twisted Pair wires, that is, high-speed digital signals with multiple rates. The transmitted data contains multiple types of data, voice, image, and video information. The transmission distance of HDSL is limited by the line ring resistance, line quality and external interference. These are determined by the different encoding methods of the HDSL transmission system. Generally, the distance of HDSL transmission without relay is 3 ~ 5 km.
HDSL used by the Industrial and Commercial Bank of Jiuquan Satellite transmitting center. The data transmission rate is 64 kbit/s, which can be increased to 2.048 Mbit/s, and the line data interface is V.35. In the HDLS data transmission circuit, the local HDLS clock and the peer HDLS clock constitute a master-slave synchronization relationship. The local HDLS sending clock is transmitted together with the sending data to the peer HDLS, the peer HDLS obtains the clock signal through demodulation and serves as the receiving clock. The receiving clock is sent to the user terminal along with the decoded data signal, which ensures the correctness of the clock signal transmission in this direction. The same is true for clock signal transmission in another direction.
3.1.2 Optical Fiber Transmission Equipment
The optical fiber transmission system from Jiuquan City to Jiuquan satellite transmission center is composed of 34 Mbit/s PDH Optical Fiber Transmission devices, including 34 Mbit/s optical terminal, 34 Mbit/s reconnecting device, 8 Mbit/s reconnecting device, 2 Mbit/s reconnecting device, and N × 64kbit/s data board. The basic principles of the optical fiber transmission system have been introduced in many textbooks. Here we will only describe the useful content in this article as follows.
1. N × 64kbit/s circuit board
The N × 64kbit/s circuit board data unit consists of a data string/parallel converter, a Data Parallel/string converter, a line data cache, and a clock signal generator. The data unit of the N × 64kbit/s circuit board is a path unit in the system column of the dynamic base group multiplexing device. N can be 1, 2, 3 ,... 31.
The data unit of the N × 64kbit/s circuit board inserts the data sent from the DTE synchronous data stream into the 2 Mbit/s time slot, and transmits the data received from the DTE to the N × 64kbit/s line, data caching can be performed to regenerate continuous data streams.
The 2MHz clock in the data unit of the N × 64kbit/s circuit board can be synchronized to the N × 64kbit/s clock from the DTE, which is always monitored during transmission, if no clock signal is detected within 30 μs, the control program is interrupted and an alarm is automatically sent to the DTE. The 2 MHz clock can also be synchronized to the sending clock of the 2 Mbit/s re er. The receiving clock is demodulated from the data stream of the 2 Mbit/s re er.
The line data interface of the N × 64kbit/s Circuit Board provides the V.35 interface. The time slot used for the data interface can be 1, 2,... 31. The TS16 time slot is generally used to control signaling. There are reverse and forward interfaces in the V.35 data interface. When used as the same-direction interface, the receiving clock is generated by the data unit, and the sending clock is obtained from the line.
2. 2 Mbit/s repeat
2 Mbit/s reentrant, which can reuse up to 31 data channels into a 2 Mbit/s digital signal. The sending clock frequency is 2 MHz in the transmission direction of 8 Mbit/s. The time division in the control channel is reused. The sending clock is divided into internal clock, receiving clock and external clock; from the receiving direction of 8 Mbit/s, convert the input digital signal conforming to the G.703 interface to the digital signal consistent with the device, complete line code decoding, and generate the clock signal in the receiving direction, it is also synchronized with the frames in the input direction, and the time slots occupied in the control path are deduplicated. Sends and receives the clock to the DTE synchronous output.
3.2 data interfaces
In the entire data transmission circuit, DDN, N × 64kbit/s circuit board, HDSL, and data terminal computer, each device's data interface is V.35, and its basic features are described as follows.
1. Electrical Properties
The electrical characteristics of V.35 interface are similar to those of balanced RS-422A, and they are similar to those of V.11 interface. Balanced transmission and differential reception of data and scheduled signals. Each signal is allocated with two cores, and the characteristic impedance of the cable is 80 ~ 120 Ω), control signal with only one core. The two ends of the balancing generator are defined as A and B. If the voltage at the end is positive relative to the voltage at the B end, it is the 0 logic. If the voltage at the end is negative relative to the voltage at the B end, it is the 1 logic. Receiver Input at both ends of the corresponding A \ 'and B \', differential receipt of the decision according to the VA-VB =-0.55V for 1 logic, VA-VB = + 0.55V for 0 logic design.
2. Mechanical Properties
V.35 interface mechanical characteristics, the 34-core connector is required to comply with ISO 2593), circuit pin allocation and functions as shown in Table 1. In actual use, some use only some of its core wire pins, so also use a connector with less cores, the rule of their own definition. The length of the wire is not limited, and the British post and telecommunications system proposed to be 60 m.
3. procedure features
For synchronous interfaces, the clock line is the most important feature in the procedure. The clock line refers to the 113, 114, and 115 circuits. The clock line plays a major role. The DTE or DCE interface must constantly use the clock from the peer clock line to correct its clock. Generally, the phase-locked loop circuit is used for clock synchronization ), to extract data correctly. The clock line requirements are as follows:
1) The sending clock of the 113 circuit is the clock transmitted from the DTE interface to the DCE interface, which is generated by the local DTE interface. As long as the DTE is valid, the 113 circuit should have an effective timing signal. In applications, 114 and 115 are required to be rolled back to 113.
2) the receiving clock of the 115 circuit is the clock transmitted from the DCE interface to the DTE interface, which is extracted from the signals sent from the local DCE device.
3) The 114 circuit sends the clock, which is the clock that the DCE interface transmits to the DTE interface, which is generated by the local DCE device.
4 remote user data transmission circuit Synchronization
4.1 clock transfer relationship of remote user data transmission circuit
To form a complete data transmission circuit, there is a problem of how the receiver can correctly decode and divide the received digital code. To correctly decode and split the acceptor, you must be able to automatically identify the sequence arrangement rules in the received bitstream and generate a timing pulse with the same timing status as that of the receiver, in this way, the sending and receiving operations can be ensured in a consistent manner. The "synchronization system" of the receiving end is used to complete this task ". It can be used to identify the time sequence of code streams and control the clock signal generator used for receiving and timing.
For the above remote user access to DDN, it is mainly the synchronization of the 2 Mbit/s adapter and the N × 64kbit/s data board, synchronization between the N × 64kbit/s Data Board and the DDN node and HDLS. To ensure full synchronization of the data transmission circuit, the synchronous clock signal must be transparently transmitted from the transmitting end to the receiving end at any transmission point of the data transmission circuit, or transparently transmit data from a point in the middle of the data transmission circuit to both ends. If the data transmission circuit cannot transmit data transparently at a certain point, a buffer should be added at this point, and there will be a buffer in the above Optical Fiber Transmission Equipment.
4.2 data transmission circuit Synchronization Process Analysis
The 64 kbit/s data transmission circuit from the Industrial and Commercial Bank of Jiuquan City to the Industrial and Commercial Bank of Jiuquan Satellite Launch Center is from Terminal A to DDN Node 2, and then from DDN Node 2 to N × 64kbit/s Data Board 2, then it is connected from the N × 64kbit/s Data Board 2 to the terminal B. All V.35 interfaces in the data transmission circuit adopt a 6-wire system, which provides six interface circuits, including 102, 103, 104, 113, 114, and 115, except 102 is a line, each other circuit is two lines.
The 64 kbit/s data transmission circuit from the Industrial and Commercial Bank of Jiuquan City to the Industrial and Commercial Bank of Jiuquan Satellite transmitting center uses the clock of DDN1 nodes as the main clock of the whole circuit.
1. Terminal A to DDN2 Node
DDN1 node to Terminal A: Terminal A is DTE, and DDN1 node is DCE. The two interfaces are directly connected using A data cable. The receiving clock is set to 115, and the sending clock is set to 114.
DDN2 node to DDN1 node: This circuit is part of the national public digital data transmission network DDN), the clock has a master-slave synchronization relationship, where the DDN1 node as the main clock, the analysis of the following synchronization problems will not be affected.
2. DDN2 node to N × 64kbit/s Data Board 2
DDN2 node to N × 64kbit/s data board 1: DDN2 node and N × 64kbit/s data board 1 are both DCE, and the two interfaces are crossly connected by data cables, connect the receiving clock 115 of the data user interface of the DDN2 node to the sending clock 113 of the N × 64kbit/s data board 1, connect the sending clock 113 of the data user interface of the DDN2 node to the receiving clock 115 of the N × 64kbit/s data board 1.
N × 64kbit/s data board 1 to 2 Mbit/s readapter 1: N × 64kbit/s data board 1 is mainly a data interface unit) can provide external clock signals of MHz, according to the PCM principle, there is a strict synchronization relationship between N × 64kbit/s data board 1 and 2 Mbit/s rejunction 1. 2 Mbit/s rejunction 1 has an external clock input, and the software can set the Sending timing of 2 Mbit/s rejunction 1 to an external clock mode. In this way, the sending clock of the DDN2 node is extracted from the N × 64kbit/s data board 1. After doubling, the clock can be provided to the 2 Mbit/s reseller 2, the same clock is used to enable N × 64kbit/s data board 1 and 2 Mbit/s rejunction 1.
2 Mbit/s repeat 1 to 2 Mbit/s Repeat 2: from the PCM principle, we can see that 2 Mbit/s repeat 1 and 2 Mbit/s Repeat 2 are master slave synchronization relationships. In the actual device, the MHz clock signal can be transparently transmitted from one end of the optical fiber transmission system to the other end after the code speed adjustment, if you set the sending clock of 2 Mbit/s Repeat 2 to line timing, then, the clock signal can be extracted from the data sent by 2 Mbit/s repeat 1 as the 2 Mbit/s Repeat 2 clock signal.
2 Mbit/s readapter 2 to N × 64kbit/s Data Board 2: According to the PCM principle, 2 Mbit/s Repeat 2 has a strict synchronization relationship with N × 64kbit/s Data Board 2, which is mainly a data interface unit) and uses the same clock signal, provided by 2 Mbit/s Repeat 2.
3. N × 64kbit/s Data Board 2 to Terminal B
The N × 64kbit/s Data Board 2 to HDLS1: N × 64kbit/s Data Board 2 and HDLS1 are both DCE, and the two interfaces are crossly connected by data cables, connect the receiving clock 115 of the N × 64kbit/s Data Board 2 data user interface to the sending clock 113 of HDLS1, connect the sending clock 113 of the N x 64 kbit/s Data Board 2 data user interface to the receiving clock 115 of the N x 64 kbit/s data board 1.
HDLS1 to HDLS2: the synchronization relationship between the two HDLS is master-slave synchronization, where HDLS1 is set to master clock and HDLS2 is set to slave clock.
HDLS2 to Terminal B: Terminal B is DTE, while HDLS2 is DCE. The two interfaces are directly connected using data cables. The receiving clock is 115, and the sending clock is 114.
In the above data transmission circuit, the DDN1 node and HDLS2 need to cycle the receiving clock 115 back to the sending clock 114. If the software is not available, you must use hardware jumpers to complete the installation at the interface, to ensure that the sending clock and receiving clock of each device in the full data transmission circuit are directly or indirectly locked on the sending clock of the DDN1 node.
5 conclusion
In addition to the preceding complex access methods, the remote user access method of the DDN Node also includes satellite communication data channels and modem, microwave communication data channels plus modem, and other complex methods, to ensure normal data transmission, the most critical issue is synchronization in the full data transmission circuit. Through the analysis of the above issues, we hope to give readers some inspiration.