A high-precision clock synchronization method for LAN based on PTP Protocol (RPM)

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1 Introduction

In distributed systems, a global time is often needed to determine the sequence of events in the system, to coordinate the transmission of various messages, and to control and monitor the state of the system. It is necessary to unify the local time of each part in the system and clock synchronization. With the widespread application of distributed simulation system and test system on the network, how to provide reliable clock service on the network becomes an important topic. And because of the system speed requirements, the accuracy of synchronization has become an important indicator.

The PTP (Precision time Protocol) protocol is a precision clock synchronization protocol defined in IEEE-1588, and the PTP protocol is designed for relatively localized, networked systems, better subnets, and relatively stable internal components. The PTP protocol is widely used in distributed systems because of its simple implementation and the advantages of less network and computing resources.

The PTP protocol can be implemented either by hardware or by software. When the implementation of the hardware can achieve the NS level of precision, the implementation of the software can usually achieve MS-level accuracy. When the software is used in the network to achieve the precision of sub-millisecond, there are many factors which cause the unreliable time synchronization. This includes the instability of the network, the caching effect of the NIC on the packet and the effect of the operating system process scheduling, which are often unpredictable and uncontrollable, resulting in the eventual failure of the clock synchronization.

In this paper, combining the characteristics of the computer and the clock synchronization mechanism of PTP protocol, a high-precision clock synchronization method is presented, which realizes the time synchronization of Guinea millisecond accuracy of LAN by constructing high-precision clock, adopting the handshake mechanism and processing the measurement results. The effect of various factors on clock synchronization is effectively solved.

　2 PTP Protocol Clock Synchronization original embedding and analysis

A simple PTP-based clock synchronization machine: The system consists of a master clock and multiple slave clocks, time synchronization mainly by the sender and receiver of the information containing the time of the timestamp, and the receiver based on the time stamp calculation of the master-slave clock time skew and time information transmitted in the network delay to achieve. To manage these time information, the PTP protocol defines four types of information, including sync (sync information), followup (Follow-up information after sync), Delayreq (Delay correction request information), and DELAYRESP (response to delay correction request information).

The difference between master and slave clocks is mainly caused by the clock skew and the delay of packets in the network transmission, and the synchronization of the master-slave clock in the PTP protocol clock synchronization mechanism is divided into two stages, offset correction and delay correction phase. As shown in Process 1.

Figure 1 PTP Protocol Clock synchronization principle

During the offset correction phase, the a stage in the diagram, the sync information is first emitted by the master clock at 1 TM time to the slave clock, and a timestamp is included in the sync information describing the estimated time of the data being emitted. Since the information contains the estimated time to emit rather than the actual time of issue, the true time of the sync information is measured and sent in subsequent followup messages. On the slave clock side, recording the true receive time of the sync information TS1, the time offset offset from the clock relative to the main clock can be computed by TM1 and TS1:

The time offset can be adjusted from the clock. However, the calculated results still contain the delay caused by the transmission of time information in the network, so the delay correction is also required.

In the delay correction phase, the B stage in the diagram, first by sending the Del ayreq information from the clock to the master clock, from the clock record to send the exact time TS2, the master clock record receives the accurate time 2 TM, and the time is returned through DELAYRESP to the slave clock. The network delay delay is calculated from the clock through these two times:

The value is used from the clock to correct it. At this time, the master-slave clock is synchronized by offset correction and delay correction.

But in the practical application, especially in the network with pure software implementation, the simple use of the above-mentioned process clock synchronization can not achieve the synchronization accuracy of sub-millisecond. This is mainly due to the cache effect of network card, the instability of networks and operating system process scheduling and other aspects of the impact.

When the information is transmitted in the network, the information is first sent to the buffer of the local network card, and the buffer is sent to the receiver's NIC when the network is idle. In this way, when the sender sends more than one message to the receiver, the information is first cached in the buffer, including the cache of the sender's network card and the cache of the receiver's network card, and all information may be received at the same time when the receiver receives the information. This leads directly to the inaccurate measurement of information reception time, which results in the failure of time synchronization.

Table 1: Deviation Measurement (unit: U S interval: 1 s)

Compared with the caching effect of NIC, the instability of network and the process scheduling of operating system are more complicated, because these two factors are uncertain and uncontrollable. The instability of the network leads to the unpredictable delay of the packet transmission in the network, which affects the accuracy of synchronization.

While the operating system uses the time slice rotation mechanism to dispatch the process, which makes it impossible to control when the time synchronization process is scheduled and when it stops, resulting in unpredictable software delay. For example, the data in table 1 is a set of data measured in a local area network, representing the main clock and the deviation from the clock, in us. During the test process, the main clock continuously sends 10 offset correction time information to every 1s from the clock, in order to ensure that the network is in a certain active state, some computers in the network open FTP download. As can be seen from the data in table 1, the data sent sequentially in each group is relatively stable, with a relative deviation of about dozens of u s, but there are some special values that differ significantly from group to group, and the data between groups differs greatly from a few ms to hundreds of MS, which makes it impossible to determine which data is reliable for clock synchronization.

After the above analysis, it is necessary to deal with the above factors, otherwise the high-precision clock synchronization can not be achieved.

　3 High-precision clock synchronization method based on PTP protocol

High-precision clocks are the basis for high-precision clock synchronization, so this method first constructs a high-precision clock. On this basis, through the analysis of PTP protocol, in order to solve the cache effect of network card, the instability of networks and the effect of operating system process scheduling on clock synchronization accuracy, a handshake mechanism is introduced on the basis of PTP protocol, and the method of filtering and linear fitting is adopted to realize the clock synchronization of millisecond precision.

　3.1 Construction of high-precision clocks

For a system, the clock can be divided into two kinds, the physical clock and the logical clock. The physical clock, also known as an absolute clock or wall clock, corresponds to the time in the real world. MS-level physical clocks are usually obtained through the computer's built-in clock chip. The relative clock refers to the system's unique clock, independent of the physical clock, but with the physical clock has a certain conversion relationship.

When the system has no interaction with the outside world, the clock in the system can be realized by logic clock. Logic clocks are simple, versatile, and can meet the requirements of most applications, and logic clocks are used in many systems.

In order to achieve high-precision timing, such as the microsecond level of timing, the general use of high-frequency crystal oscillator implementation. In fact, the computer CPU itself with a high-precision clock, for a 2GHz CPU, this clock timing accuracy of up to 0.5ns. And the Windows system provides some interfaces to get the frequency of the CPU and the count of the timer after the computer is powered on, so you can construct a high-precision logical clock through these API interfaces, and you can convert to physical time units.

Here, the T0 represents the count value of the CPU timer, T represents the deviation of the logical time relative to the CPU count, and the current logical time t can be constructed as follows:

And the modification of the current logic time t can be achieved by modifying the DT.

When you need to use physical time units to measure logical times, you can convert them accordingly. The conversion formula is as follows:

where T ' is the logical time in us, and F is the CPU clock oscillation frequency, which can be obtained by the API provided by Windows.

Although the CPU clock frequency is very high, but because the CPU count value also needs to consume time, so does not achieve the CPU clock level accuracy. The experimental results show that the logic clock constructed by this method can achieve the accuracy of 1us. This can meet the needs of most occasions.

　3.2 Handshake mechanism

For the caching effect of the network card, it is not possible to solve the problem by increasing the time interval between two transmissions. The interval small does not have the function of the isolation two transmission, the interval is large, the clock synchronization will also be affected by the network instability and the operating system process scheduling. The use of the handshake mechanism and blocking socket sockets can effectively solve this problem. That is, when the receiving party receives the information, it returns a confirmation message, and the sender sends the next message only after receiving the acknowledgement from the recipient. This isolates two information transmissions so that the receiver does not receive all the information from the sender.

　3.3 Timing Requirements for clock synchronization

The instability of the network and the effect of operating system process scheduling may cause the clock synchronization to fail. However, the analysis shows that, despite these factors, it is possible to achieve high-precision clock synchronization. In table 2 below, the 5 sets of data (10 groups were tested randomly selected 5 groups of data), the test environment is the same as the data test environment in table 1, the same applies the handshake mechanism to avoid the caching effect of the network card, but in the test process, the main clock to send two sets of data from the clock interval of 10ms.

As can be seen from the data in the table, the measured master-slave clock deviation is stable, approximately dozens of us, except for some of the larger singular values, which indicates that it is possible to achieve 0.1ms precision clock synchronization in this period of time.

Table 2: Deviation Measurement (unit: U s interval: 1 0ms)

The above analysis shows that in order to complete the clock synchronization operation in the case of relatively stable network and operating system, the time required for synchronization is as short as possible, but in order to obtain stable and reliable data, sufficient data is needed for analysis and processing.

　3.4 Data processing algorithms

In order to obtain valid data from the measured data, the data needs to be processed. First, there are some significant differences in the data, which need to be found and filtered to eliminate the impact. In addition, to minimize the variance of the remaining valid data, it is necessary to fit the data.

Assuming data [1:n] is the measured N data, data ' [1:m] is filtered and the filtering process can be performed as follows. where m = n-m-N.

Fm,n first to sort the data, so that the difference between the values of the array on both sides, the elimination of M-small values and n large values, you can achieve the filtering processing of the data. M and n are variable parameters, depending on the size of the data and the degree of stability of the data.

Since data ' [1:m] tends to be a horizontal line, the data can be fitted in a least squares line using line y = C. This is where the data is processed in the mean value. The fitting can be carried out as follows.

This obtains the best fit value C from the N data.

　3.5 Clock Synchronization Complete steps

According to the above conclusions, and combined with the PTP protocol clock synchronization mechanism, a reliable clock synchronization scheme can be designed, as shown in the process.

(1) The master clock in tm1[1] sends the sync information to the slave clock, and records the exact moment of transmission tm1[1], and then sends the sync information to the slave clock in the FOL lowup message at the moment Tm1[1] sent. After receiving the SYN C information from the clock, record the exact time of receiving ts1[1] and return the confirmation message OK.

(2) Repeat the process n times, so that from the clock to get n clock information sent and received time Tm1[1:n] and ts1[1:n], will tm1[1:n] and ts1[1:n] do poor, get the master-slave clock n offset value offset [1:n].

(3) The offset [1:n] for filtering and linear fitting, to obtain a best fit value of all data offset, and use this value to offset from the clock, that is, a phase in the diagram.

(4) by sending Delayreq information from the clock to the master clock and recording the exact time of transmission ts2[1], the master clock receives delayreq information and records the exact time of receipt tm2[1], and returns the DELAYRESP in subsequent tm2[1] to the slave clock.

(5) Repeat the 4th step of the process M, from the clock to get 2M clock information, tm2[1:n] and ts2[1:n], two arrays do not get the M master-slave clock delay message delay [1:m].

(6) The delay information delay [1:M] for filtering processing and linear fitting, to obtain a delay information of the best fit value of delay, and the use of this value to delay correction from the clock, that is, the B stage in the diagram.

Figure 2 Complete steps for clock synchronization.

When the network is relatively stable and the computer load is small, m = n = 10,m = n = 2 can satisfy the sub-millisecond accuracy requirement.

After the above six steps, that is completed a master-slave clock synchronization, in order to avoid the clock accumulation error on the system synchronization accuracy of the impact, can cycle the above process, to maintain the system synchronization.

4 Experimental results and analysis

The test uses 4 identically configured computers, using a switch to build a local area network, of which 1 are used as master clocks and the rest as slave clocks.

The logic clock uses a high-precision clock constructed using the above principles, with a CPU frequency of 1.79553GHz and a t,= T *6 /F converted to a logic clock in U S. To obtain a certain amount of data, take m = n = 10,m = n = 2. In order to keep the network in a certain active state, on the computer to open the F T P download, the switch load around 5mb/s.

The test is similar to the clock synchronization process, after the master-slave clock synchronization, the main clock sends the sync information to the slave clock, and in the subsequent followup information sends the sync information in the exact moment TM sent over, from the clock record sync information accurate receive time TS. Because the clock is synchronized at this time, the TS-TM is the time delay delay T in the transmission, compares this value delay T with the delay information in the delay correction of the best fit value delay, can be obtained the synchronization effect of master-slave clock.

The randomly selected 10 groups of data are listed in Table 3.

Table 3 Test Results

As can be seen from table 3 test results, the maximum absolute error is -25.3us and the average error is only -4.23us. The synchronization accuracy of the master-slave clock 0.1ms is realized. This shows that the effect of various factors on the accuracy of clock synchronization is effectively solved by the handshake mechanism, the filtering of data and the processing of linear fitting.

　5 concluding remarks

By analyzing the characteristics of time information transmission between master and slave clocks, a clock synchronization scheme which can achieve sub-millisecond accuracy is designed on the basis of PTP clock synchronization mechanism. and tested, the solution is practical.

At present, the clock synchronization method has been successfully used in the general test simulation platform of the Institute to timestamp the various information transmitted in the Platform, and the virtual serial communication device is used to coordinate the message transmission.

Source: Just Friends

A high-precision clock synchronization method for LAN based on PTP Protocol (RPM)