A simple makefile Tutorial

http://blog.163.com/weidao_xue/blog/static/2045410462012102222755897/Ext.: http://www.paeonia.me/Blog/2012/05/13/%E4%B8%80%E4%B8%AA%E7%AE%80%E5%8D%95%E7%9A%84makefile%E6%95%99%E7%A8%8B/

Write Makefile is a very convenient method of compiling, because used to put all the code in a file, does not show the advantages of make, when the source code into a number of source files, makefile is necessary. The following is a simple Makefile tutorial, refer to from a Makefile Tutorial. As the text says, this tutorial is intended to allow beginners to quickly get started and write their own makefile to maintain small and medium-sized projects.

A simple example with K&r C in 4.5 that example: the main program (MAIN.C), the function code (GETOP.C, STACK.C, getch.c), the header file (calc.h).
In general, we will use

1	gcc -o calc main.c getch.c getop.c stack.c -I.

To compile. -I. Refers to GCC in the current directory (.) Find the include file below. If we do not need to makefile, in the test-modify-debug process, if we do not want to re-knock the compiler command, we must constantly in the terminal press the up and down key to find the final compilation instructions. Unfortunately, this compilation method has two drawbacks: 1. When you lose the compilation instructions or change the computer, this will be very inefficient; 2. When we modify only one. c file, each time it will have to recompile all the files, which is very time-consuming and not cost-effective. Now it's time to cut into the subject.

The simplest makefile notation:
Version 1

12	calc: main.c getch.c getop.c stack.c    gcc -o calc main.c getch.c getop.c stack.c -I.

If you write these statements to a file called Makefile or makefile, and then enter make in the terminal, she will compile as you requested in the makefile. Note: The first row does not have any parameters, just the colon (:) lists the required files in the compilation, and when any of the files in the first row changes, make knows that Calc needs to be recompiled. Now we have solved the problem 1, do not have to press the arrow up and down, but for the problem 2 is still not a good solution. Note that it is important to have a tab in front of GCC and a tab before any instructions, or make will strike.

Make things a little more efficient:
Version 2

12345

CC = gccCFLAGS = -I.calc: main.c getch.c getop.c stack.c    $(CC) -o calc main.c getch.c getop.c stack.c $(CFLAGS)

Now we have defined two constants cc and Cflags. These are the special constants that communicate with make and let makes know how we compile the. c file. CC is used by the C compiler, and Cflags is a compilation parameter. Make will compile the. c file separately, and then generate the executable file Calc.

This form of makefile is very effective in small projects, but there is a regret: the changes in the include file. If we modify the Calc.h file, make is not recompiled. c files, in fact we need to recompile. To solve this problem, we must tell make all the. c files depend on the. h file. We can add a rule to the makefile:
Version 3

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CC = gccCFLAGS = -I.DEPS = calc.h%.o: %.c $(DEPS)    $(CC) -c -o [email protected] $< $(CFLAGS)calc: main.o getch.o getop.o stack.o    $(CC) -o calc main.o getch.o getop.o stack.o $(CFLAGS)

First, the macro defines Deps, which declares the. h file on which the. c file depends. Then we define a rule that generates an. o file for all. c files. Rule description: the. o file relies on the. h file declared in the. c file and Deps, in order to generate the. o file, make needs to compile the. c file using the compiler declared in CC. -C means the object file is generated,-o [email protected] means that the compiled generated file is named with the above%.O,$< refers to the first item in the dependency relationship (%.C) Cflags the same definition as before.

Finally, to simplify, we use special macros to define [email protected] and $^, respectively, to represent the colon (the left and right sides of the:). In order for all the rules in make to be more generic, in version 4, we took all the include files as part of the Deps, and all the object files as part of obj:
Version 4

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CC = gccCFLAGS = -I.DEPS = calc.hOBJ = main.o getch.o getop.o stack.o%.o: %.c $(DEPS)    $(CC) -c -o [email protected] $< $(CFLAGS)calc: $(OBJ)    $(CC) -o [email protected] $^ $(CFLAGS)

If we want to place the. h file under the Include directory, the. c file is placed in the SRC directory and some local libraries are placed in the Lib directory, and we want to tidy up the. o file to avoid clutter in the entire directory. In version 5, the Include,lib directory is defined and the object file is placed in the obj subdirectory of the SRC directory, along with any libraries we want to include (such as the Math library-LM). This makefile will be placed in the SRC directory. It is important to note that a clean rule has been added to this release to allow make clean to run. The directory structure is as follows:

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idir =: /include CC = gcc CFLAGS =-i$ (idir)   ODIR = obj ldir =: /lib   LIBS =-lm   _deps = calc.h DEPS = $ (patsubst%,$ (idir)/%,$ ( _deps))   _obj = main.o getch.o getop.o stack.o OBJ = $ (patsubst%,$ (ODIR)/%,$ (_obj))   $ (ODIR)/%.O:%.C $ (DEPS)      $ (CC)-c-o [email  protected] $< $ (CFLAGS)   Calc: $ (OBJ)      Gcc-o [email protected] $^ $ (CFLAGS) $ (LIBS)   . Phony:clean   clean:      rm -F $ (ODIR) /*.O *~ Core $ (idir)/*~

Where the Patsubst function contains 3 parameters: a pattern to match, what to replace it with, and a space-delimited string to be processed.

Now we have a good makefile, according to this, we can maintain small and medium-sized projects. Of course we can add some more complicated rules and even create some rules. For more information on Makefile and make please refer to GNU do Manual.

A simple makefile Tutorial