About Mac and PHY of Ethernet

Q: How to implement a single chipEthernetMicrocontroller? A: The trick is to connect the microcontroller and Ethernet Media to the Controller (MacAnd physical interface transceiver (Phy) Integrated into the same chip, which can remove many external components. This solution enables good matching between MAC and PHY, and reduces the number of pins and chip area. The Single-Chip Ethernet microcontroller also reduces power consumption, especially when the power loss mode is used. Q: What is an Ethernet MAC? A: Mac is the media access controller. Ethernet MAC is defined by IEEE-802.3 Ethernet standards. It implements a data link layer. The latest Mac supports both 10 Mbps and Mbps. Generally, it implements the MII interface. Q: What is MII? A: MII is the media independent interface, which is the Ethernet industry standard defined by the IEEE-802.3. It includes a data interface and a management interface between MAC and PHY (figure 1 ). Data interfaces include two independent channels used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals. The management interface is a dual-signal interface: one is the clock signal, and the other is the data signal. Through the management interface, the upper layer can monitor and control the phy. To sum up, MII can be understood as the exchange interface between MAC and PHY. There are two types of interfaces. One is the management interface, which is used to manage the phy, For example, the settings of the PHY register. Another type is the data interface, which is used to send and receive data with the phy. For example, the am335x data interface of TI has 15 signal lines and the management interface has 2 signal lines. Data Interface, pin definition:

Management Interface pin definition:

Q: What is an Ethernet PHY?

Answer: PHY is a physical interface transceiver that implements the physical layer. The IEEE-802.3 standard defines the Ethernet Phy. It complies with the specification used in the IEEE-802.3k for 10 BaseT (14th) and 100 basetx (24th and 25th.

 

Q: Why is it difficult to integrate Ethernet MAC and PHY on a single chip?

A: PHY integrates a large number of analog hardware, while Mac is a typical full-digital device. Chip area and analog/digital hybrid architecture are the reasons why Mac is first integrated into the microcontroller and PHY is left off the chip. The more flexible and higher-density chip technology can already achieve single-chip integration between MAC and PHY.

Q: Do I need other components besides the RJ-45 interface?

A: other components are required. Although PHY provides the vast majority of analog support, in a typical implementation, external 6 and 7 discrete components and a LAN insulation module are still required. The insulation module generally uses a 1:1 transformer. The main function of these components is to protect the PHY from damage caused by electrical errors.

Q: Why is the implementation of 10baset and 100 basetx PHY different?

A: The group descriptions of the two implementations are essentially the same, but their signaling mechanisms are completely different. The purpose is to prevent a hardware implementation from easily processing two speeds. 10baset adopts Manchester encoding and 100basetx adopts 4b/5b encoding.

Q: What is Manchester encoding?

A: Manchester encoding, also known as Manchester phase encoding, implements each bit through phase changes (figure 2 ). Generally, the rising edge in the middle of a clock cycle is "1", and the falling edge is "0 ". The phase changes at the end of the cycle are negligible, but sometimes they may need to be included, depending on the value of the previous bit.

Q: What is 4B/5b encoding?

A: 4b/5b encoding is a block encoding method. It encodes a 4-bit block into a 5-bit block. This enables the five-bit block to always contain at least two "1" conversions, so the clock synchronization can always be performed within a five-bit block. This method requires an additional 25% overhead.

Mac and PHY of the NIC

The network adapter works on the last two layers of OSI. The physical layer and the data link layer define the electrical and optical signals, line statuses, clock benchmarks, data encoding, and circuits required for data transmission and reception, provides standard interfaces to data link layer devices. The Physical Layer Chip is called Phy. The data link layer provides addressing mechanisms, data frame construction, data error check, transfer control, and standard data interfaces to the network layer. The data link layer chip in the ethernet card is called the Mac controller. Many NICs work together. The relationship between them is that the PCI bus is connected to the Mac bus, the Mac is connected to the phy, And the PHY is connected to the network cable (of course, it is not directly connected, there is also a pressure change device ).

How to transmit data and communicate with each other between PHY and Mac. Connect Mac and PHY through the standard MII/gigamii (Media independed interfade) interface defined by IEEE. This interface is defined by IEEE. The MII interface controls all the data and data on the network.

This article is reprinted from csdn. The original user's link is not found. Here, I would like to express my gratitude to the original user. I am studying the relationship between PHY and Mac. I feel that this article is very well written. I have collected it and recommended it to you.