About GDT LDT IDT

(From: http://blog.csdn.net/lihenair/article/details/5168396)

Intel Architecture Software Developer's Manual Volum 3A: SystemProgramming Guide

 

The segment descriptor is used to convert the virtual addresses of code, Data, stack, and task status segments into linear addresses and specify the segment type. The segment descriptor only appears in the local and global descriptor tables.

The 16-bit length character is put in the segment register. Part of the pointer is used to select a descriptor in the global or local descriptor table to determine a specific memory segment in a virtual address space, it is called the selector.

 

LDT is used to describe the code segment, data segment, and stack segment of the corresponding program. GDT describes the system segment, including the operating system code and data.

 

GDT LDT GDTR LDTR

Global and Local Descriptor Tables

When the protection mode is enabled, all memory access goes through the Global description table (GDT) or an optional local description table (LDT ). The entries in these tables are called segment descriptors. The segment descriptor provides the access permissions of the segment base address and segment, the segment type and usage information.

Each segment descriptor has a corresponding segment selector. A segment selector provides its index in GDT or LDT (the offset of the corresponding segment descriptor), and a global/local flag (determines whether the selector points to GDT or LDT) and access permission information.

 

One byte in the access segment must provide a segment separator and an offset ). The segment selector provides the access segment descriptor (in GDT or LDT ). The segment descriptor and processor are used to obtain the segment base address in a linear space. The offset provides a location in bytes relative to the base address. This mechanism can be used to access any valid code, data zone, or stack segment, and provide segments that can be accessed according to the current priority (CPL) when the processor is working. CPL is defined as the protection level of the currently executed code segment.

 

The base address of the linear address of GDT is located in the GDT register (GDTR); the base address of the linear address of LDT is located in the LDT register (LDTR;

 

Global and Local Descriptor Tables in IA-32e Mode

 

System Segments, Segment Descriptors, and Gates

In addition to code segments, data segments, and stack segments, the architecture also defines two system segments: Task status segments (TSS) and LDT. GDT is not considered as a segment because it cannot be accessed through the segment selector and segment descriptor. TSSs and LDTs have segment descriptors to define them.

 

The architecture also defines a set of special descriptors called call gates, interrupt gates, trap gates and task gates. These gates provide methods to protect system programs and handler. System programs and handler may work on different priorities from applications and many programs. For example, a call door request can provide a method to access a program in the code segment, and this code segment may have a lower priority than the code segment on the right at the same level or number. In order to allow the caller to access the program, the call process provides a selection character for the caller. The processor then checks the access permissions of the call door to compare the priority CPL of the call door and the target code segment pointed to by the call door.

 

If the target code segment is allowed to be accessed, the processor will get the segment selector of the target code segment and the offset of the code segment in the calling door. If the request needs to change its priority, the processor switches to the stack of the target priority. The segment selector of the new stack is obtained from the TSS of the current task. You can easily switch between 16-bit and 32-bit code segments, and vice versa.

 

Task-State Segments and Task Gates

TSS defines the execution environment status of the task. Includes general purpose registers, segment registers, EFLAG registers, EIP registers, and stack segment selector and pointer with a privilege level of 0, 1, and 2. TSS also includes the segment selector representing the LDT task and the base address of the page structure hierarchy.

All programs executed in protection mode run in the context of the task (becoming the current task. The segment selector of the current task TSS is stored in the task register. The simplest way to switch tasks is to use call or jump to new tasks. At this point, the TSS segment selector of the new task is given by the CALL or JMP command. When switching tasks, the processor performs the following operations:

1. Save the status of the current task in the current TSS

2. Load the segment selector of the new task to the task register.

3. Access the new TSS through the task descriptor in GDT

4. Load the new task status from the new TSS to the general purpose register, segment register, LDTR control register (base address of the Page Structure Level), EFLAG register and EIP register.

5. Start executing the new task

The task can also be accessed by the task gate. The task gate is similar to the call door, except that it provides methods for accessing TSS rather than code segments.

 

Interrupt and Exception Handling

External interruptions, soft interruptions, and exceptions are handled by the Interrupt Descriptor Table (IDT. IDT stores a set of gate descriptors that provide methods for access interruption and exception handling programs. Like GDT, IDT is not a segment. The linear address representing the IDT base address contains the IDT register (IDTR.

The gate descriptor in IDT can be an interrupt, a trap, or a task gate descriptor. In order to access the interrupt or exception descriptor, the processor first accepts an interrupt vector (Interrupt number) from the internal hardware, External Interrupt Controller or INT, INTO, INT 3, BOUND ). The interrupt vector provides indexes in IDT. If the selected door descriptor is an interrupt door or trap door, the corresponding processing function is accessed by operations similar to the call door of a request. If the descriptor is a task gate, the processing function is accessed by switching the task.

 

Memory-Management Registers

The processor provides four memory management registers (GDTR, LDTR, IDTR, TR ).

 

Global Descriptor Table Register (GDTR)

The GDTR register stores the real-Mode 32-bit base address and 16-bit limit length of GDT. The base address specifies the linear address of GDT 0 bytes, and the table limit length specifies the number of bytes in the table.

After the processor is powered on or restarted, the base address is set to 0 by default and the length limit is set to 0 FFFFH. The new base address is added to GDTR when operating in the processor initialization protection mode.

 

Local Descriptor Table Register (LDTR)

The LDTR register stores the LDT's 16-bit segment selector, base address (Protection Mode 32-bit), segment length, and descriptor attributes. The base address specifies the linear address of GDT 0 bytes, and the table limit length specifies the number of bytes in the table. The segment containing LDT must have a segment descriptor in GDT.

When the task is switched, LDTR automatically loads the segment selector and descriptor of the new task LDT.

After the processor is powered on or restarted, the base address is set to 0 by default and the length limit is set to 0 FFFFH. The new base address is added to GDTR when operating in the processor initialization protection mode.

 

Memory Management Overview

The memory management function is divided into two parts: segmentation and paging. Segmentation provides a mechanism to isolate individual code, data, and stack modules. Therefore, multiple programs (or tasks) can be executed on the same processor without being disturbed by other processors. Paging provides a mechanism for implementing regular page requests. The virtual memory system (the part of the program execution environment can be mapped to the physical address as needed) can also be used to split multiple tasks.

Each system must define a GDT that can be used by all programs and tasks in the system. (Optional) one or more ldts can be defined. For example, a single LDT can be defined for each separate task, or some or so tasks share the same LDT.

GDT itself is not a segment; instead, it is a data structure in a linear address space. The linear base address and limit length of GDT must be loaded into the GDTR register. The base address of GDT must be 8-byte aligned in exchange for the best processor performance. The length of GDT is measured in bytes. Like other segments,