About I2C and SPI bus protocols

About I2C and SPI bus protocols Iicvs SPI

Currently, in the low-end digital communication application field, we can see IIC (Inter-Integrated Circuit) and SPI (serial peripheral interface) everywhere. The reason is that these two communication protocols are very suitable for close-range and low-speed chip communication. Philips (for IIC) and Motorola (for Spi) have developed these two standard communication protocols for different backgrounds and market needs.

IIC was developed in 1982 to provide a simpler way to interconnect the CPU and peripheral chips in the TV. TV sets are one of the earliest embedded systems, and the initial embedded systems use memory-mapped I/O to interconnect controllers and peripheral devices. To realize memory ing, the device must connect to the data line and address line of the microcontroller in parallel. This method requires a large number of lines and extra address decoding chips when connecting multiple peripherals, which is inconvenient and costly.

To save microcontroller pins and additional logic chips and make printed circuit boards simpler and cheaper, the Philips laboratory in the Netherlands developed 'inter-integrated circuit', IIC or IIC, A bus protocol that uses only two wires to connect all peripheral chips. The initial standard defined bus speed was 100 kbps. Several revisions were made, mainly in 1995 kbps and 400 1998 Mbps in 3.4.

There are indications that the SPI bus was first launched in 1979, and Motorola integrated the SPI bus on their first microcontroller chip changed from a 68000 microprocessor. The SPI bus is a four-line External Bus (relative to the internal BUS) of the microcontroller ). Unlike IIC, SPI does not have clear text standards, but is only a fact standard. The implementation of communication operations is only abstract description, chip manufacturers and drivers communicate with each other through data sheets and application notes.

SPI

For experienced Digital Electronics Engineers, using SPI to connect two digital devices is quite intuitive. SPI is a four-signal line protocol ():

§ Sclk: serial clock (output from Master );

§ MoSi; Simo: Master output, slave input (output from Master );

§ Miso; somi: Master input, slave output (output from slave );

§ SS: slave select (active low, outputfrom master ).

SPI is a [Single-master] communication protocol, which means that only one central device in the bus can initiate communication. When the SPI main device wants to read/write [slave device], it first lowers the SS line corresponding to the [slave device] (SS is valid for low level ), next, we start to send the working pulse to the clock line. In the corresponding pulse time, the [main device] sends the signal to MoSi for "writing", and at the same time, we can sample miso for "reading ", for example:

SPI has four operation modes: Mode 0, Mode 1, Mode 2, and mode 3. The difference between them is that it defines which edge conversion (toggles) of the clock pulse outputs the signal, which Edge Sampling input signal and the stable level value of the clock pulse (that is, whether the clock signal is high or low when it is invalid ). Each mode is characterized by a pair of parameters, which are called clock polarity cpol and Clock Phase cpha.

[Master/Slave devices] the same operating parameters-sclk, cpol, and cpha must be used for normal operation. If multiple [slave devices] use different operating parameters, the [Master devices] Must be reconfigured between different [slave devices. The main content of the above SPI bus protocol. The SPI does not specify the maximum transmission rate, and there is no address scheme. The SPI does not specify the communication response mechanism and no traffic control rules. In fact, the SPI [master device] does not even know whether the specified [slave device] exists. These communication controls must be implemented independently through the SPI protocol. For example, to connect a [command-Response Control] decoder chip with SPI, a more advanced communication protocol must be implemented based on SPI. SPI is not concerned with the electrical characteristics of physical interfaces, such as the standard voltage of signals. At the beginning, most SPI applications use intermittent clock pulses and transmit data in bytes. However, many variants now implement continuous time pulses and data frames of any length.

IIC

Unlike a single SPI main device, an IIC is a bus of multiple main devices. An IIC does not have a physical chip to select a signal line, but does not have an arbitration logic circuit. Only two signal lines are used-'seriial data' (SDA) and 'serial clock' (SCL ). IIC Protocol provisions:

§ 1. Each IIC device has a unique seven-digit device address;

2. The data frame size is 8 bytes;

§ Third, some data bits in the data (FRAME) are used to control the start, stop, direction (read/write) and response mechanisms of communication.

IIC data transmission rates include standard (100 Kbps), fast (400 Kbps), and high-speed (3.4 Mbps). other variants implement low-speed (10 Kbps) and fast + mode (1 Mbps ).

Physically, the iic bus consists of two signal lines and one ground line. The two signal lines are transmitted in two directions. For more information, see. The IIC protocol standard specifies that the device that initiates a communication is called the master device. After the master device initiates a communication, all other devices are slave devices.

The IIC communication process is roughly as follows. First, the master device sends a start signal, which is like shouting to all other devices: Please note! Then other devices start to listen to the bus to prepare for receiving data. Then, the master device sends a data frame with a seven-bit device address plus one-bit read/write operation. After the device receives the data, compare whether the address itself is the target device. If the comparison is not consistent, the device enters the waiting status and waits for the arrival of the stop signal. If the comparison is consistent, the device sends a response signal, acknowledge, to respond.

When the primary device receives a response, it starts to send or receive data. The data frame size is 8 bits, followed by a response signal. The master device sends data and replies from the device. On the contrary, the master device receives data and the master device responds. When data transmission is complete, the master device sends a stop signal to release the bus to other devices, and the other devices return to the initial status.

Based on the physical structure of the IIC bus, the start and stop signals on the bus must be unique. In addition, the IIC Bus Standard specifies that the data conversion of the SDA line must be in the low-level period of the SCL line. The data on the SDA line is stable during the high-level period of the SCL line.

In terms of physical implementation, both the SCL line and the SDA line are open-drain, and a voltage source is added through the pull-up resistor. When the line is grounded, the line is logical 0. when the line is released and idle, the line is logical 1. Based on these features, IIC devices ONLY "ground the line" for bus operations-the output logic is 0.

The IIC bus design uses only two lines, but it is perfect to achieve seamless communication between any number of devices elegantly. Let's imagine what will happen if two devices send messages to both the SCL and SDA lines at the same time.

Based on the IIC bus design, there is no possibility of level conflict on the line. If one device sends logic 0 and the other sends logic 1, only logic 0 is displayed on the line. That is to say, if a level conflict occurs, the sending logic 0 is always the "Winner ".

The physical structure of the bus also allows the master device to read data while writing data to the bus. In this way, any device can detect conflicts. When two master devices compete for the bus, the "Winner" does not know about the competition. Only the "loser" finds a conflict-when it writes a logic 1, read 0-and withdraw from the competition.

10-bit device address

Any IIC device has a 7-bit address. Theoretically, there are only 127 different IIC devices. In fact, there are far more types of IIC devices than this limitation. The probability of IIC devices with the same address on a bus is quite high. To overcome this restriction, many devices use a dual address-a 7-bit address and a pin address (external configuration pins ). IIC standards also pre-know this restriction and propose a 10-bit address scheme.

The 10-bit address scheme has two impacts on the IIC protocol:

§ 1. The address frame is two bytes long. The original address frame is one byte;

§ Second, the first five most effective bits of the first byte are used as the 10-bit address identifier, which is "11110 ".

In addition to the 10-bit address identifier, the standard also reserves some address codes for other purposes, as shown in the following table:

Clock stretch

In IIC communication, the master device determines the clock speed. Because the clock pulse signal is explicitly sent by the main device. However, when the slave device cannot keep up with the speed of the master device, the slave device needs a mechanism to request the master device to be slower. This mechanism is called clock stretching, and is implemented based on the particularity of the i² C structure. When the device needs to reduce the transmission speed, it can press the clock line to force the main device to enter the waiting status until the device releases the clock line, the communication continues.

High speed mode

In principle, using the pull-up resistor to set logic 1 limits the maximum transmission speed of the bus. Speed is one of the factors that limit bus applications. This also shows why high-speed mode (3.4 Mbps) is introduced ). Before initiating a high-speed transmission, the master must first send a specific "High Speed Master" signal in low-speed mode (for example, fast mode. To shorten the signal cycle and increase the speed of the bus, an additional I/O buffer must be used in high-speed mode. In addition, bus arbitration can be blocked in high-speed mode. For more information, see the bus standard documentation.

IIC vs spi: who is the winner?

Let's compare the key points of IIC and SPI:

1. Consumption of bus topology, signal routing, and hardware resources

IIC only needs two signal lines, and the standard SPI must have at least four signals. If there are multiple slave devices, more signals are needed. Although some SPI variants only use three wires-sclk, SS, and bidirectional miso/MoSi, the SS cables must be one-to-one with the slave device. In addition, if the SPI is to implement a multi-master device structure, the bus system requires additional logic and lines. The only problem with using IIC to build a system bus is a limited 7-bit address space, but the new standard for this problem has been resolved-using a 10-bit address. From the first point, IIC is an obvious winner.

Second, data throughput/transmission speed

If the application must use high-speed data transmission, SPI is an inevitable choice. Because SPI is full duplex, IIC is not. SPI does not define a speed limit. Generally, the implementation can reach or even exceed 10 Mbps. The maximum speed of IIC is fast + mode (1 Mbps) and high speed mode (3.4 Mbps). The subsequent mode also requires an additional I/O buffer, which is not always easy to implement.

Third, elegance

IIC is often called more elegant than SPI. To be fair, we prefer to think that the two are equally elegant and robust. The elegance of IIC lies in its characteristics. It uses a lightweight architecture to implement multi-master device arbitration and device routing. However, for engineers, it is more difficult to understand the bus structure and the bus performance is not high.

The advantage of SPI is that its structure is quite intuitive and simple, easy to implement, and has good scalability. The simplicity of SPI is not elegant, because a useful communication platform needs to be built using SPI and specific communication protocol software. That is to say, in order to obtain the unique characteristics of SPI and the features that IIC does not have-high-speed performance, engineers need to do more work. In addition, this kind of custom work is completely free, which also shows why SPI has no official standard. Both IIC and SPI provide good support for communication between low-speed devices. However, SPI is suitable for data stream applications, while IIC is more suitable for multiple master devices of "Byte devices.

Summary

In the digital communication protocol cluster, IIC and SPI are often referred to as "small" protocols. Compared with Ethernet, USB, SATA, PCI-Express, and other bus with transmission speeds up to hundreds of gigabytes per second. However, what we can't forget is the purpose of various bus. The "big" protocol is used for communication between the entire system outside the system, and the "small" protocol is used for communication between chips in the system, there is no indication that the "big" protocol is necessary to replace the "small" protocol. The existence and prevalence of IIC and SPI embodies the philosophy of "Enough is good. In response, IIC and SPI are so popular that they are essential tools for any embedded engineer.