Add Fiq interrupts and related issues in Uboot

This article mainly describes the problems encountered in adding Fiq interrupts in Uboot and the corresponding solutions.

First, explain the hardware and software environment of the project. Hardware, using s3c2440 as the main control chip, external serial port, network card and other equipment. On the software side, the master chip runs the Uboot program after power-on, then burns the application through the network port to run in RAM. In order to keep the device in a controlled state, it is necessary to add the remote control program in the Uboot and the application separately, the remote control program uses the Fiq interrupt to realize. The modification of Uboot program is mainly in \arch\arm\cpu\arm920t\start.s file and Arch\arm\lib\board.c file.

Problem:

What did the processor do after the Fiq interrupt occurred?

After an outage, the ARM processor needs to process the current instruction, and then automatically completes the following things:

1. Save the current program status register CPSR to the Backup program status register Spsr_fiq in Fiq mode (the inverse process cannot be completed automatically when the execution interrupt returns).

2. Reduce the program counter PC (R15) value by 4 to the link register R14_fiq (that is, LR) in Fiq mode.

3. Force the value of the PC to ox0000001c (the entry address of the Fiq in the exception vector table) and jump to that address for execution.

Description

The

1.ARM processor defines undefined_instruction (0x00000004), Software_interrupt (0x00000008), Prefetch_abort (0x0000000c), data _abort (0x00000010), IRQ (0x00000018), Fiq (0x0000001c) and other anomalies, when the exception occurs, the chip will automatically complete the above operation and jump to the corresponding address to execute, Where the chip on the power after the automatic jump to 0x00000000 this address execution, the general will be at these unusual addresses to store the jump instruction, in order to achieve the subsequent operation.

1 _start:    b    start_code2    Ldr    pc, _undefined_instruction3     Ldr    pc, _software_interrupt4    Ldr    pc, _prefetch_abort5     Ldr    pc, _data_abort6    LDR    pc, _not_used7     Ldr    pc, _IRQ8     Ldr    pc, _fiq

Where Start_code is the startup code.

What do I need to do after jumping to the exception vector table?

After the processor forces the PC to point to 0x0000001c, and then jumps to the _fiq label again, the user needs to write a program to do the following things:

1. Calculate the return address of the program. Because the ARM9 uses a 5-level pipeline structure, and the execution stage of the program is at the 3rd level of the pipeline, the PC always points to the next two instructions executing the instruction, that is, the executing instruction address is PC-8 (the program executes to the high address direction). Since Fiq occurs when the processor finishes executing instructions, the PC value is also updated, which is pc=pc+4, and the processor automatically stores the PC value minus 4 in the R14_fiq register. The address returned by the program should be the next instruction in the instruction being processed when FIQ occurs, so the address in R14_fiq is reduced by 4, which is the address that the program should return.

2. Optionally save the Register LR (which is changed when using the BL instruction), R0-r12 (all universal registers, if the change cannot revert to the state before the FIQ occurs, the values of these registers are generally protected in the stack, which requires the stack of the FIQ mode to be set beforehand in the startup code).

3. Jump to the interrupt handler function, note that BL (save the next instruction address, can be returned), and not use B (do not save the next instruction address, cannot return).

4. After executing the interrupt handler function, you need to restore the LR, r0-r12 out stack.

5. Pass the value of LR to the PC and jump to the next instruction when Fiq occurs (using subs PC, LR, #0的目的是为了将SPSR_fiq中的值恢复至CPSR中).

1 Fiq: 2     Subs LR, LR, #43     stmfd sp!, {r0-r12,lr}4    bl roger_test     5     LDMFD sp!,{r0-R12,LR}6     Subs pc, LR, #0

Third, the location of the interrupt processing function?

The processor jumps to the startup code after power-up and initializes the relevant registers and peripherals sequentially. The Fiq interrupt is opened at the end of the Board_init_r () function of ARCH\ARM\LIB\BOARD.C, at which time the initialization of the processor is complete and is already in the C locale.

Add Fiq interrupts and related issues in Uboot