Address translation mechanism

Address: http://sist.sysu.edu.cn/os-course/course/04-2-2.htm

 

In the previous section, you have learned how Windows 2000/XP organizes a 32-bit virtual address space. The following describes how to map these address spaces to real physical pages. We will also describe what the system will do when the address translation cannot find the address of the physical storage, it also explains how Windows 2000/XP manages physical memory through a workset and page box database.

User applications are handled in a 32-bit virtual address format. The CPU uses the data structure created and maintained by the Memory Manager to convert the virtual address to the physical address. Figure 4-11 maps three consecutive virtual pages to 4-11 of three discontinuous physical pages. the dotted line connecting the virtual page and page table items shows the indirect relationship between the virtual page and the physical memory. Virtual addresses are not directly mapped to physical addresses, but each virtual address is related to a structure called "page table item" (PTE, the physical address of the virtual address ing is included in this structure. Next, we will explain in detail how Windows 2000/XP implements the above address ing.

1. Virtual Address Translation

Windows 2000/XP uses a two-level page table structure in the X86 architecture to convert virtual addresses to physical addresses. (The system running the physical address extension (PAE) kernel uses a three-level page table. The following discussion assumes that the system is not a PAE system .) A 32-bit virtual address is interpreted as three independent components-page Directory Index, page table index, and byte index-which are used to locate the index that describes the page ing structure. As shown in Figure 4-12, the page size and the width of the page table items determine the width of the page Directory and page table index. For example, in x86 systems, because a page contains 4096 bytes, the byte index is determined to be 12-Bit Width (212 = 4096 ).

 

The following is a basic step for virtual address translation:

1) the memory management hardware device locates the page Directory of the current process. During each process switchover, the operating system sets a dedicated CPU register to notify the address of the directory of the hardware device's new process page.

2) The page Directory Index is used to point out the location of the page Directory Entry (PDE) in the page Directory. The pageframenumber (PFn) in the page Directory describes the location of the page table required to map the virtual address.

3) The page table index is used to specify the position of the page table item in the page table. The page table describes the location of the virtual page in the physical memory.

4) The page table item is used to determine the position of the page box. If the required page is valid, the page table item contains the page number of a page in the physical memory. The corresponding virtual page contains the physical page box. If the page table item indicates that the required page is invalid, the Fault Handler of the Memory Manager locates the page and tries to make it valid. (For details, refer to "page missing handling".) If the invalid page cannot be valid (for example, due to a protection error), the fault handling program will generate an access violation or error check.

5) when the page table item points to a valid page, the byte index is used to locate the address of the data needed in the physical page.

Now we have a general impression on the page Directory, page table, and page table items. The following describes their detailed structure.

2. page Directory

Each process has a separate page Directory, which is a special page created by the Memory Manager and used to map the location of all the page tables of the process. The physical address of the Process page Directory is saved in the kprocess block. In fact, in the x86 system, it is also mapped to the address 0xc0300000 (in the system running the PAE kernel, It is mapped to oxc06000000 ).

The reason why the CPU knows the location of the page Directory page is that the CPU has a dedicated register (Cr 3 in x86 system), and the operating system places the physical address of the page Directory in this register. A process switchover at any time will generate a thread different from the current thread. The content of this private register will be refreshed by the corresponding information of the core process block of the new process. Because different threads of the same process share the same process address space, switching between different threads of the same process will not update the physical address of the page Directory.

The page Directory is composed of page Directory items (PDE). Each page Directory item is 4 bytes long (8 bytes long in the system running the PAE kernel ), describes the status and position of all the page tables of a process. (The page table is created as needed, so the page Directory of most processes only points to a small part of the page table .) The format of the page Directory items is not repeated here, because it is roughly the same as the hardware page table items.

In x86 systems, 1024 page tables (2048 PAE systems) are required to describe a total of 4 GB of virtual address space. The page Directory of the Process maps these page tables to 1024 page Directory items. Therefore, the page Directory Index must have a 10-Bit Width (212 = 1024 ).

3. Process page table and system page table

 

Before referencing a byte using the byte offset in the page, the CPU must first find the page containing the required byte. Therefore, the operating system constructs another page containing ing information in the memory. The page containing the ing information is called "page table ". Because Windows 2000/XP provides a private address space for each process, and the address ing of each process varies, therefore, each process has its own unique page table set to map private address spaces.

The page table that describes the system space is shared by all processes. When the process is just created, the page Directory item of the system space is initialized to point to the existing system page table. However, as shown in Figure 4-14, the system space of each process is different. For example, if a paging buffer pool extension request is assigned a new system page table, the memory manager does not update all process page directories so that they all point to the new system page table, instead, the process page Directory is updated only when the process accesses a new virtual address.

4. page table items

As mentioned above, a page table consists of a page table item (PTE) array. You can use the "! PTE command to analyze page table items. Valid page table items (This will be discussed here, and invalid page table items will be described later) have two main fields: the page box number of the physical page containing data, or the page number of the physical address of a page in the memory. It is also a flag that describes the page status and protection restrictions, as shown in 4-15. The reserved bits marked in Figure 4-15 are only used when the page table items are invalid (these bits are explained by the software ). Table 4-8 briefly describes the meanings of the items in a valid page table defined by hardware.

In the x86 system, the hardware page table includes a modified bit and an access bit. If the physical page appears as neither read nor written, the access bit is zero. When a header is read/written, the processor will "1 ". Only when a certain header is written, the modified bit will be set to "1" by the processor ". In addition to the two flags, the X86 architecture also has a write bit to provide page write protection-when this bit is zero, the corresponding page is read-only; when this bit is "1", the corresponding page can be read and written. If the write bit of a page is zero, a thread tries to write to it, which will cause memory management exceptions. Access to the fault handling program of the Memory Manager will be detailed in the following section) you must determine whether this thread can perform write operations on this page (for example, if this page is indeed marked as "Copy at write time") or whether an access violation occurs.

In a multi-processor x86 system, the hardware page table item also has an additional write bit implemented by the software, mainly for the fast table (TLB) of the page table item on different processors) eliminate latency when refreshing. This indicates that a page has been written by a thread running on multiple processors.

On the x86 hardware platform, the page table items are always 4 bytes (the system that can run PAE is 8 bytes), so that each page table contains 1024 (512 PAE systems) page table items (4096 bytes per page, 4 bytes per page table item), and therefore 1024 (512 PAE system items) 4 MB (2 MB for PAE System) pages can be mapped.

In the x86 system, the page table index is 10 bits (PAE is 9 bits), and a maximum of 1024 page table entries can be indexed (PAE is 512 ). Windows 2000/XP provides 4 GB virtual address space. Therefore, you need to map multiple page tables to all address spaces. In the x86 system, each page table can map 4 MB data pages (PAE is 2 MB). Therefore, 1024 page tables (4 GB/4 MB) are required to map 4 GB address space. For the PAE system, 2048 page tables (4 GB/2 MB) are required ).

5. byte Index

Once the memory manager finds the required physical page, it must also find the required data on the page. This is the purpose of introducing byte index fields. The Byte index field tells the offset of CPU data on the page. In x86 systems, the byte index is 12-bit wide and can index up to 4096 data bytes (exactly the size of one page ).

6. Fast table TLB

 

Two Queries are required for each address change: one is to find the correct page table in the page directory, and the other is to find the correct items in the page table. If two additional memory queries are performed for each access to the virtual address, this will seriously degrade the system performance. Therefore, most CPUs use the high-speed cache technology during address translation. The x86 processor provides high-speed cache in the form of an array of associated storage, called the express table (translation lookaside buffer, TLB ). The so-called associated storage, such as TLB, is a vector. Its storage unit can be read at the same time and compared with the target value. In TLB, vectors contain the ing of most recently used virtual pages to physical pages (4-16) and page protection types for each page. Each item in TLB is similar to a cache item. Its identifier stores part of the virtual address, the data part stores a physical page number, a protected domain, and a valid package usually have a modified bit, which indicates the status of the page corresponding to the cached page table item. If the global bit of a page table item is set to "wide (used for system space pages visible to all processes), The TLB item is still valid during process switching.
Because common virtual addresses are most likely recorded in TLB, the change from virtual addresses to physical addresses is fast and memory access is reduced. If a virtual address is not in TLB, it may still be in memory, but it needs to be accessed multiple times to find it. If a virtual page has been invoked out of memory, or the Memory Manager has changed the page table items, the memory manager must explicitly set the corresponding TLB items to invalid. When the process accesses this virtual page again, a page disconnection occurs. The memory manager re-calls the page back to the memory and re-creates an item for it in TLB.
To maximize code versatility, the memory manager treats all page table items equally, wherever possible, whether maintained by hardware or software. For example, when a page table item changes from invalid to valid, the memory manager calls a kernel routine. The task of this routine is to install the new page table item. ntlb as required by the architecture. In x86 systems, no software intervention is required to mount the processor to TLB, so this part of the code is NOP.