Advantages of systemopengl from the usage of Logic Data Types

The difference between the line network and the variable Reg may be the most difficult for beginners of Tilde. Sometimes you have to use Reg, but sometimes you have to use wire.

In systemopengl, we will see that you can replace reg or wire type with logic type in the past.

In fact, logic improves the reg data type so that it can be driven by continuous assignments, gate units, and modules in addition to being a variable. Obviously, logic is a more appropriate name.

Here is an example of Ram modelling to illustrate the above problem. We will implement it by using OpenGL and systemopengl respectively.

// Ram modelling in OpenGL
1 Module Mema (r_wb, ADDR, D_q );
2 Input R_wb;
3 Input [ 7 : 0 ] ADDR;
4 Inout [ 7 : 0 ] D_q;
5
6 Wire R_wb;
7 Wire [ 7 : 0 ] ADDR, D_q;
8 Reg [ 7 : 0 ] Mem [ 0 : 255 ];
9
10 Assign D_q = (R_wb) ? Mem [ADDR]: 8 ' Hz;
11  
12 Always @ (R_wb Or ADDR)
13 If ( ! R_wb)
14 Mem [ADDR] = D_q;
15 Endmodule // Ram modelling in systemopengl 1 Module Mema (r_wb, ADDR, D_q );
2 Input R_wb;
3 Input [ 7 : 0 ] ADDR;
4 Inout [ 7 : 0 ] D_q;
5
6 Logic r_wb;
7 Logic [ 7 : 0 ] ADDR Logic[7:0]D_q;// Gotcha! Shocould be declared: wire [] D_q;
8 Logic [ 7 : 0 ] Mem [ 0 : 255 ];
9
10 Always @ (R_wb Or ADDR)
11 If ( ! R_wb)
12 Mem [ADDR] = D_q;
13 Else
14 D_q = Mem [ADDR];
15 Endmodule

As shown above, all the other variables can be declared as logic without distinguishing the differences between the network and the variable Reg. Is the advantages of systemopengl obvious?

Other advantages of systemopengl, please refer to: http://www.doulos.com/knowhow/sysverilog/tutorial

It is worth noting that logic cannot have multiple structural drivers. That is to say, logic cannot assign values to the same variable using continuous assignment statements or output port connections more than once. This is because there is no final conclusion about the MultiDrive variables similar to those of the network. Therefore, if you assign a value to a variable in these ways, you cannot assign a value to the variable using the procedure assignment statement.

For example, the above Ram ModellingCodeWhen modeling the inout bidirectional bus, you need to use the network type. (Compared to the verilog-1995, many of the new systemopengl feature require only one driver for the variable !)

The following code contains rows 3rd and 4th. Logic-type "exception" is assigned values by two instantiation operations, so the compiler reports an error. The solution is to define the exception as a wire type.

// Multiple driver example 1 Module Multiple_drivers ( Output Logic exception,
2 Input Logic [ 7 : 0 ] A, B );
3 Is_zero inst0 (exception, B );
4 Is_greater inst1 (exception, a, B );
5 Endmodule
6
7 Module Is_zero ( Output Logic zero,
8 Input Logic [ 7 : 0 ] X );
9 Always @ (X)
10 If (X = 0 ) Zero = 1 ;
11 Else Zero = 0 ;
12 Endmodule
13
14 Module Is_greater ( Output Logic greater,
15 Input Logic [ 7 : 0 ] X, y );
16 Always @ (X, y)
17 If (X > Y) Greater = 1 ;
18 Else Greater = 0 ;
19 Endmodule