AHCI vs NVMe

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While there are a number of high-tier SSD products switched to PCIe interface to break through the SATA interface of the bandwidth of the décolleté, but the controller design and SATA interface SSD, the old AHCI controller interface, the advantage is that most of the operating system has natively supported AHCI drivers, compatibility of high-energy support of the absolute partial Operating system and the main board platform, the AHCI controller interface does not fully perform the performance advantages of the PCI Express interface and NAND Flash particles.

The AHCI Controller interface (Advanced Host controller Interface) is a very old technical specification for the PCI era, mainly the mechanical HDD that is written on the spinning disc, such as joining NCQ (Native Command Queuing) Technology, the optimization of the hard drive of the information distribution, the access order for the most efficient sequencing to reduce the distance of the robot arm moved, into the province and extended the effect of the drive longevity, but the design is not for the SSD product.

The NVMe controller interface is particularly well-developed for PCI Express interfaces and NAND Flash features, and NVMe can handle the highest 6萬4千個 command Queues command column at the same time, each instruction column can contain up to 6萬4千個 instructions, fully capable of making NAN D Flash Parallel Reading advantages. The AHCI controller interface can only handle 1 command Queues instruction columns at the same time, each instruction column can contain up to 32 instructions, which makes IOPS read performance significantly behind the NVMe.

In addition, the NVMe controller interface supports the MSI-X (interrupts processing), which was first introduced in the PCIE 3.0 technical specification, and has been added to the interrupts steering for the ability to be interrupted. The old AHCI controller only supports interrupts in the MSI, the device only allocates 1 addressing and can only handle 1 interrupts at a time, allowing the single core to be accessed in the multi-core processor environment.

The NVMe controller can be assigned up to 2048 interrupts processing, each of which has its own unique target, which makes the system different processor cores can simultaneously access the SSD device, a difference that makes NVMe and AHCI in IOPS and read delays in the There is a huge gap.

When the required knew address is not in the register, the AHCI controller interface requires an extra charge of 6-9 instruction cycles to complete the reading, costing 12000 ~ 18,000 CPU Cycles, resulting in delays of about 2.5 ~ 4μs, while the NVMe controller interface requires only 2 extra instruction, the cost of the 4,000 CPU Cycles, the NVMe SSD device has a lower latency, reducing the CPU resource charges to the performance of the calculation is obviously improved.

There is also a huge performance difference between AHCI and NVMe when dealing with a large number of files, and when the AHCI controller interface reads commands, the command parameters are accessed twice without a system memory, and NVMe only needs to be accessed by a single Bytes system memory, which makes IOPS throughput significantly Improve. In addition, the AHCI controller interface requires synchronous locking when the command is issued, and the NVMe controller does not need to synchronize locks, which will effectively improve parallel reading and multi-thread performance.

Like the IDE interface, the SATA connect port and the AHCI interface have completed a history task, and the NVMe controller interface will become the mainstream standard for the future storage interface, based on the PCI Express protocol, in conjunction with the future NAND Flash technology development.

NVMe and AHCI Storage Interface Comparison

	AHCI	NVMe
Maximum Queue Depth	1 Command Queue Commands per Q	64K Queues 64K Commands per Q
Un-cacheable Register accesses	12,000-18,000 CPU Cycles Wasted	~ 4,000 CPU Cycles wasted
Msi-x and Interrupt	Single Interrupt No steering	2048 Interrupt with steering support
Parallelism & Multiple Threads	Requires Synchronization Lock To issue command	No Locking Required
Efficiency for 4KB Commands	Command parameter require Serialized host DRAM fetches	Command parameters in one Bytes Fetch

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AHCI vs NVMe