Alibaba Cloud Resource Management Framework (III)

We will introduce the read/write of SDRAM in two main lines: address line and data line.

First, the address is online and started on FPGA. The latency is 500 subtle. Then the address counter cntwr waits until the latency is us plus 1

(Else if (delay_done) cntwr <= cntwr + 1 'b1)

Add the address register ADDR to 1 until 63.

(Else if (! Wr_done & cntwr = 6 'h3f) ADDR <= ADDR + 1 'b1)

That is to say, 32 milliseconds, the address line is added with 1, but this address line is not finally sent to the SDRAM, but only generates temporary address information.

Bytes ----------------------------------------------------------------------------------------------------------

In the data line, FPGA starts, and the latency is 500 subtle. To write data to the first-in-first-out (write is a noun, indicating that this first-in-first-out is used to write data), the counter CNT is set to pull the valid write pin at 5 hours, at the same time, when the data register wr_dinr is added to 1 and CNT and 0d, the write effective pin is lowered. At the same time, the data register stops adding 1 and ends data writing. A total of 8 data records are written. So eight reciprocating writes!

(Else if (! Wr_done & (cntwr> 6'h05) & (cntwr <= 6'h0d) begin

Wrf_dinr <= wrf_dinr + 1 'b1)

Bytes ------------------------------------------------------------------------------------------------------------------------------

Once the number of data records written to the first batch reaches 8, the system is activated to write the SDRAM request signal sdram_wr_req (high)

(Assign sdram_wr_req = (wrf_use> = 9 'd8 )&~ Syswr_done )).

Sdram_wr_req is effective, and the read/write state machine runs to the 'W _ active state.

(Elseif (sdram_wr_req & sdram_init_done) begin

Work_state_r <= 'W _ active ).

So as to go To the 'W _ write status. Once this status is entered, the sdram_wr_ack signal will be activated.

(Assign sdram_wr_ack = (work_state = 'W _ write) | (work_state = 'W _ WD) & (cnt_clk_r <9 'd8) & (cnt_clk_r> = 9 'd0 ));)

This signal controls whether the data in the write FIFO is transmitted to the Q pin. Therefore, after the sdram_wr_ack is valid, the data in the write FIFO is transmitted to Q and then transmitted to the sys_data_in data register connected to it. As the data enters the 'W _ write status, the Data Writing module sdram_wr_data is started, and the data is sent to the data port of the SDRAM chip.

(Elseif (work_state = 'W _ write) | (work_state = 'W _ WD) & (cnt_clk <9 'd8) & (cnt_clk> = 9 'd0 )))

Sdr_din <= sys_data_in ;)

(After this status is completed once, enter the waiting status idel to re-judge the current information. If yes, enter this status again. If the status does not meet this status requirement, go to another status)

Certificate -----------------------------------------------------------------------------------------------------------------------------------

Look at the address line. When we enter the 'W _ write status, we do not know where the ADDR has been counted. However, when we reach 'W _ write, the sys_addr generated by the current ADDR is split into rows, and the column value is transmitted to the address line of the SDRAM.

(Sdram_addr_r <= {

4 'b0010,

Sys_addr [8: 0]};

)

At the same time as the transfer address, the data will be written into it! In this way, the transfer address will not stop until the address line is full. The era of writing data to SDRAM is over.

(Else if (ADDR = 22 'h3fffff)

Wr_done <= 1 'b1 ).

Certificate ---------------------------------------------------------------------------------------------------------------------------------------

When the ground line is full, the syswr_done is activated.

(Assign syswr_done = wr_done)

In addition, because the data in the read FIFO storage is 0, the signal line sdram_rd_req that writes data to the read FIFO storage is activated.

(Assign sdram_rd_req = (rdf_use <= 9 'd256) & syswr_done ))

This signal is valid, and the state machine enters the read SDRAM data status 'W _ read

(Else if (sdram_rd_req & sdram_init_done) begin

Work_state_r <= 'W _ active; // read SDRAM

Sys_r_wn <= 1 'b1;

)

In this status, the read data request signal sdram_rd_ack is activated.

(Assign sdram_rd_ack = (work_state_r = 'W _ RD) & (cnt_clk_r> = 9 'd0) & (cnt_clk_r <9 'd8 );)

If this signal is valid, the address line starts from 0 and increases by 1.

(Else if (wr_done & neg_rdack)

ADDR <= ADDR + 1 'b1;) // neg_rdack is the pulse generated after sdram_rd_ack is valid.

Sent to the SDRAM address line at the same time (after this status is completed once, enter the waiting status idel and re-judge the current information. If yes, enter this status again. If the status does not meet this status requirement, go to another status)

(Sdram_addr_r <= {

4 'b0010, // A10 = 1, set write to allow pre-Charging

Sys_addr [8:0] // column address

};

)

That is to say, each time this status is temporary, the SDRAM address line will be updated with 1. Compared with Data Writing, when reading data, the address is continuous, which is equivalent to traversing all the addresses. Each time the SDRAM address line is updated, the data on the SDRAM Data Bus is updated. Pass the data to the serial sending module

(Else if (work_state = 'W _ RD) & (cnt_clk> = 9 'd0) & (cnt_clk <9 'd8 ))

Sdr_dout <= sdram_data ;)

Send to PC host machine (about serial port sending module, make up your brain)

This article is from "Hi, jiashuo !" Blog, please be sure to keep this source http://jiashuo.blog.51cto.com/10830673/1707384

Alibaba Cloud Resource Management Framework (III)