ALTERA DE2 verilog HDL Learning Note 01 program parallelism

Recently began to learn Verilog HDL language, right on the hand there is a DE2 from the seniors borrowed an FPGA development board. Take advantage of the holidays to learn.

Because there are some C-language basics, it is very fast to look at Verilog HDL syntax. The biggest difference between it and C is that the HDL language has a lot of module, and the module is a parallel relationship . But in some modules the interior is executed sequentially, such as begin and always.

The following is verified by a simple led flashing module. The program has 1 top-module and 4 different delay sub-module. 4 Sub-module is executed in parallel.

led0_module.v

Module Led0_module
(
    clk, Rst_n, Led_out
);

    Input CLK;
    Input rst_n;
    Output led_out;
    
    Parameter t10ms = "d20_000_000;
     
    reg [24:0] count;
    
    Always @ (Posedge CLK or Negedge rst_n)
        if (!rst_n)
            count <= ' D0;
         else if (count = = t10ms)
            count <= ' D0;
         Else
            Count <= count + 1 ' B1;
             
    Reg Rled_out;

    Always @ (Posedge CLK or Negedge rst_n)
        if (!rst_n)
            rled_out <= 1 ' b0;
         else if (Count >= ' D0 && count < d5_000_000)
            rled_out <= 1 ' B1;
         else
            rled_out <= 1 ' b0;
            
    Assign led_out = rled_out;

	 
Endmodule

led1_module.v

1bit led output When Rst_n is pushed led_out =0 module led1_module (<span style= "White-space:pre" > </span>c


Lk,rst_n,led_out);
<span style= "White-space:pre" > </span>input CLK;
<span style= "White-space:pre" > </span>input rst_n;
<span style= "White-space:pre" > </span>output led_out; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>parameter T10MS
=25 ' d20000000;
<span style= "White-space:pre" > </span>reg [24:0] count; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>always @ ( Posedge CLK or Negedge rst_n) <span style= "White-space:pre" > </span>if (!rst_n) <span style= "White-space:
Pre "> </span>count<=25 ' D0; <span style= "White-space:pre" > </span>else if (count = = t10ms) <span style= "White-space:pre" > </sp
An>count<=25 ' D0; <span style= "White-space:pre" > </span>else  <span style= "White-space:pre" > </span>count<=count+1 ' B1;
<span style= "White-space:pre" > </span>reg rled_out; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>always @ ( Posedge CLK or Negedge rst_n) <span style= "White-space:pre" > </span>if (!rst_n) <span style= "White-space:
Pre "> </span>rled_out<=1 ' B0;  <span style= "White-space:pre" > </span>else if (Count >= ' B0 && count < d10000000) <span
style= "White-space:pre" > </span>rled_out<=1 ' B1; <span style= "White-space:pre" > </span>else  <span style= "White-space:pre" > </span>rled
_out<=1 ' B0; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>assign led_out =
Rled_out;


 Endmodule

led2_module.v 
 

1bit led output When Rst_n is pushed led_out =0 module led2_module (<span style= "White-space:pre" > </span>c


Lk,rst_n,led_out);
<span style= "White-space:pre" > </span>input CLK;
<span style= "White-space:pre" > </span>input rst_n;
<span style= "White-space:pre" > </span>output led_out; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>parameter T10MS
=25 ' d20000000;
<span style= "White-space:pre" > </span>reg [24:0] count; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>always @ ( Posedge CLK or Negedge rst_n) <span style= "White-space:pre" > </span>if (!rst_n) <span style= "White-space:
Pre "> </span>count<=25 ' D0; <span style= "White-space:pre" > </span>else if (count = = t10ms) <span style= "White-space:pre" > </
Span>count<=25 ' D0; <span style= "White-space:pre" > &LT;/SPAN&GT;ELSE&NBsp


<span style= "White-space:pre" > </span>count<=count+1 ' B1;
<span style= "White-space:pre" > </span>reg rled_out; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>always @ ( Posedge CLK or Negedge rst_n) <span style= "White-space:pre" > </span>if (!rst_n) <span style= "White-space:
Pre "> </span>rled_out<=1 ' B0;  <span style= "White-space:pre" > </span>else if (Count >= ' B0 && count < d15000000) <span
style= "White-space:pre" > </span>rled_out<=1 ' B1; <span style= "White-space:pre" > </span>else  <span style= "White-space:pre" > </span>rled
_out<=1 ' B0; <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>assign led_out =
Rled_out;


 Endmodule

led3_module.v 
 

Module Led3_module (    CLK, Rst_n, led_out);
    Input CLK;
    Input rst_n;
    Output led_out;
         Parameter t10ms = + ' d20_000_000;
         reg [24:0] count;          always @ (Posedge CLK or Negedge rst_n)         if (!rst_n)   &N Bsp
        count <= ' D0;
        ELSE if (count = = t10ms)             count <= ' D0;
        else             Count <= count + 1 ' B1;


                 Reg Rled_out;     always @ (Posedge CLK or Negedge rst_n)         if (!rst_n)         & nbsp
  rled_out <= 1 ' b0;         ELSE if (Count >= ' d15_000_000 && count < ' d20_000_000)             rled_out <= 1 ' B1;
        else             rled_out <= 1 ' b0;


                 Assign led_out = Rled_out;
 Endmodule

 Main program FOREVER_LED.V 
 

Module forever_led (<span style= "White-space:pre" > </span>clock_50,key,ledg);
<span style= "White-space:pre" > </span>input clock_50;
<span style= "White-space:pre" > </span>input [0:0] key;
<span style= "White-space:pre" > </span>output [3:0] ledg;
<span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>wire led0_out;
<span style= "White-space:pre" > </span>led0_mudule U0 <span style= "White-space:pre" > </span> ( <span style= "White-space:pre" > </span>.clk (clock_50), <span style= "White-space:pre" > </span >.rst_n (key), <span style= "White-space:pre" > </span>.led_out (led0_out) <span style= "White-space:
Pre "> </span>);
<span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>wire led1_out; <span style= "White-space:pre" > </span>led1_mudule U1 <span style= "White-space:pre" > </SPAN> (<span style= "White-space:pre" > </span>.clk (clock_50), <span style= "White-space:pre" > </span>.rst_n (key), <span style= "White-space:pre" > </span>.led_out (led1_out) <span style= "
White-space:pre "> </span>);
<span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>wire led2_out;
<span style= "White-space:pre" > </span>led2_mudule U2 <span style= "White-space:pre" > </span> ( <span style= "White-space:pre" > </span>.clk (clock_50), <span style= "White-space:pre" > </span >.rst_n (key), <span style= "White-space:pre" > </span>.led_out (led2_out) <span style= "White-space:
Pre "> </span>);
<span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span>wire led3_out;
<span style= "White-space:pre" > </span>led3_mudule U3 <span style= "White-space:pre" > </span> ( <span style= "whitE-space:pre "> </span>.clk (clock_50), <span style=" White-space:pre "> </span>.rst_n (Key), < Span style= "White-space:pre" > </span>.led_out (led3_out) <span style= "White-space:pre" > </span> ); <span style= "White-space:pre" > </span> <span style= "White-space:pre" > </span> <span
style= "White-space:pre" > </span>assign ledg[3:0]={led0_out,led1_out,led2_out,led3_out}; <span style= "White-space:pre" > </span> endmodule

I have to DE2 pin assignment graphs:

After downloading, you can see 4 different time-delay LED lights flashing, again emphasizing the parallel relationship ~