Altera megafunction Wizard: % lpm_divide %

You use Altera's megafunction to generate the "divider" Wizard, now you will see like that follows:

// Megafunction Wizard: % lpm_divide %
// Generation: Standard
// Version: wm1.0
// Module: lpm_divide

// ================================================ ======================================
// File name: div31.v
// Megafunction name (s ):
// Lpm_divide
//
// Simulation library files (s ):
// LPM
// ================================================ ======================================
//************************************** **********************
// This is a wizard-generated file. Do not edit this file!
//
// 7.1 build 178 06/25/2007 sp 1 SJ full version
//************************************** **********************

// copyright (c) 1991-2007 Altera Corporation
// your use of Altera Corporation's design tools, logic Functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files ), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera program license
// subscribe agreement, altera javascore function license
// agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. please refer to the
// applicable agreement for further details.

// Synopsys translate_off
'Timescale 1 PS/1 PS
// Synopsys translate_on
Module div31 (
Clock,
Denom,
Numer,
Quotient,
Remain );

Input clock;
Input [15:0] denom;
Input [30: 0] numer;
Output [30: 0] quotient;
Output [15:0] remain;

Wire [30: 0] sub_wire0;
Wire [15:0] sub_wire1;
Wire [30: 0] quotient = sub_wire0 [30: 0];
Wire [] remain = sub_wire1 [];

Lpm_divide lpm_divide_component (
. Denom (denom ),
. Clock (clock ),
. Numer (numer ),
. Quotient (sub_wire0 ),
. Remain (sub_wire1 ),
. ACLR (1' B0 ),
. Clken (1 'b1 ));
Defparam
Lpm_divide_component.lpm_drepresentation = "Signed ",
Lpm_divide_component.lpm_hint = "lpm_remainderpositive = true ",
Lpm_divide_component.lpm_nrepresentation = "Signed ",
Lpm_divide_component.lpm_pipeline = 1,
Lpm_divide_component.lpm_type = "lpm_divide ",
Lpm_divide_component.lpm_widthd = 16,
Lpm_divide_component.lpm_widthn = 31;

Endmodule

// ================================================ ======================================
// CNX File Retrieval info
// ================================================ ======================================
// Retrieval info: Private: intended_device_family string "Stratix II"
// Retrieval info: Private: private_lpm_remainderpositive string "true"
// Retrieval info: Private: private_maximize_speed numeric "-1"
// Retrieval info: Private: synth_wrapper_gen_postfix string "0"
// Retrieval info: Private: using_pipeline numeric "1"
// Retrieval info: Private: version_number numeric "2"
// Retrieval info: constant: lpm_drepresentation string "Signed"
// Retrieval info: constant: lpm_hint string "lpm_remainderpositive = true"
// Retrieval info: constant: lpm_nrepresentation string "Signed"
// Retrieval info: constant: lpm_pipeline numeric "1"
// Retrieval info: constant: lpm_type string "lpm_divide"
// Retrieval info: constant: lpm_widthd numeric "16"
// Retrieval info: constant: lpm_widthn numeric "31"
// Retrieval info: used_port: clock 0 0 0 input nodefval clock
// Retrieval info: used_port: denom 0 0 16 0 input nodefval denom [15 .. 0]
// Retrieval info: used_port: numer 0 0 31 0 input nodefval numer [30 .. 0]
// Retrieval info: used_port: quotient 0 0 31 0 output nodefval Quotient [30 .. 0]
// Retrieval info: used_port: remain 0 0 16 0 output nodefval remain [15 .. 0]
// Retrieval info: CONNECT: @ numer 0 0 31 0 numer 0 0 31 0
// Retrieval info: CONNECT: @ denom 0 0 16 0 denom 0 0 16 0
// Retrieval info: CONNECT: quotient 0 0 31 0 @ quotient 0 0 31 0
// Retrieval info: CONNECT: remain 0 0 16 0 @ remain 0 0 16 0
// Retrieval info: CONNECT: @ clock 0 0 0 clock 0 0 0 0 0
// Retrieval info: Library: LPM. lpm_components.all
// Retrieval info: gen_file: type_normal div31.v true
// Retrieval info: gen_file: type_normal div31.inc false
// Retrieval info: gen_file: type_normal div31.cmp true
// Retrieval info: gen_file: type_normal div31.bsf true
// Retrieval info: gen_file: type_normal div31_inst.v true
// Retrieval info: gen_file: type_normal div31_bb.v true
// Retrieval info: lib_file: LPM

Bytes --------------------------------------------------------------------------------------------------------------------------

Bytes --------------------------------------------------------------------------------------------------------------------------

The question is: we can't use this wizard to synthesize by DC, thereforce, we must use OpenGL to design the divider by ourself.

Another method is as follow:

// module declaration
module lpm_divide (
numer, // the numerator (required)
denom, // the denominator (required)
clock, // clock input for pipelined usage
ACLR, // asynchronous clear signal
clken, // clock enable for pipelined usage.
quotient, // quotient (required)
remain // remainder (required)
);

// Global parameter Declaration
Parameter lpm_widthn = 31; // width of the numer [] and Quotient [] port. (required)
Parameter lpm_widthd = 16; // width of the denom [] and remain [] port. (required)
Parameter lpm_nrepresentation = "Signed"; // the representation of numer
Parameter lpm_drepresentation = "Signed"; // the representation of denom
Parameter lpm_pipeline = 1; // Number of clock cycles of latency
Parameter lpm_type = "lpm_divide ";
Parameter lpm_hint = "lpm_remainderpositive = true ";

// Input port Declaration
Input [lpm_widthn-1: 0] numer;
Input [lpm_widthd-1: 0] denom;
Input clock;
Input ACLR;
Input clken;

// output port declaration
output [lpm_widthn-1: 0] quotient;
output [lpm_widthd-1: 0] remain;

// internal register/signal declaration
Reg [lpm_widthn-1: 0] quotient_pipe [lpm_pipeline + 1:0];
Reg [lpm_widthd-1: 0] remain_pipe [lpm_pipeline + 1:0];
Reg [lpm_widthn-1: 0] tmp_quotient;
Reg [lpm_widthd-1: 0] tmp_remain;
Reg [lpm_widthn-1: 0] not_numer;
Reg [lpm_widthn-1: 0] int_numer;
Reg [lpm_widthd-1: 0] not_denom;
Reg [lpm_widthd-1: 0] int_denom;
Reg [lpm_widthn-1: 0] t_numer;
Reg [lpm_widthn-1: 0] t_q;
Reg [lpm_widthd-1: 0] t_denom;
Reg [lpm_widthd-1: 0] t_r;
Reg sign_q;
Reg sign_r;
Reg sign_n;
Reg sign_d;
Reg [8*5: 1] lpm_remainderpositive;

// Local integer Declaration
Integer I;
Integer rsig;
Integer pipe_ptr;

// Internal tri Declaration
Tri0 ACLR;
Tri0 clock;
Tri1 clken;

Wire I _aclr;
Wire I _clock;
Wire I _clken;
Buf (I _aclr, ACLR );
Buf (I _clock, clock );
Buf (I _clken, clken );

// Component instantiations
Lpm_hint_evaluation EVA ();

// Initial construct Block
Initial
Begin
// Check if lpm_widthn> 0
If (lpm_widthn <= 0)
Begin
$ Display ("error! Lpm_widthn must be greater than 0. \ n ");
$ Finish;
End
// Check if lpm_widthd> 0
If (lpm_widthd <= 0)
Begin
$ Display ("error! Lpm_widthd must be greater than 0. \ n ");
$ Finish;
End
// Check for valid lpm_nrepresentation Value
If (lpm_nrepresentation! = "Signed") & (lpm_nrepresentation! = "Unsigned "))
Begin
$ Display ("error! Lpm_nrepresentation value must be \ "signed \" or \ "unsigned \".");
$ Finish;
End
// Check for valid lpm_drepresentation Value
If (lpm_drepresentation! = "Signed") & (lpm_drepresentation! = "Unsigned "))
Begin
$ Display ("error! Lpm_drepresentation value must be \ "signed \" or \ "unsigned \".");
$ Finish;
End
// Check for valid lpm_remainderpositive Value
Lpm_remainderpositive = Eva. get_parameter_value (lpm_hint, "lpm_remainderpositive ");
If (lpm_remainderpositive = "true ")&&
(Lpm_remainderpositive = "false "))
Begin
$ Display ("error! Lpm_remainderpositive value must be \ "True \" or \ "false \".");
$ Finish;
End

For (I = 0; I <= (lpm_pipeline + 1); I = I + 1)
Begin
Quotient_pipe [I] <={ lpm_widthn {1 'b0 }};
Remain_pipe [I] <={ lpm_widthd {1 'b0 }};
End

Pipe_ptr = 0;
End

// Always construct Block
Always @ (numer or denom or lpm_remainderpositive)
Begin
Sign_q = 1' B0;
Sign_r = 1' B0;
Sign_n = 1' B0;
Sign_d = 1' B0;
T_numer = numer;
T_denom = denom;

If (lpm_nrepresentation = "Signed ")
If (numer [lpm_widthn-1] = 1 'b1)
Begin
T_numer = ~ Numer + 1; // numer is negative number
Sign_n = 1' B1;
End

If (lpm_drepresentation = "Signed ")
If (denom [lpm_widthd-1] = 1 'b1)
Begin
T_denom = ~ Denom + 1; // denom is negative numbrt
Sign_d = 1' B1;
End

t_q = t_numer/t_denom; // get quotient
t_r = t_numer % t_denom; // get remainder
sign_q = sign_n ^ sign_d;
sign_r = (t_r! = {Lpm_widthd {1 'b0 }})? Sign_n: 1' B0;
// pipeline the result
tmp_quotient = (sign_q = 1 'b1 )? (~ T_q + 1): t_q;
tmp_remain = (sign_r = 1 'b1 )? (~ T_r + 1): t_r;

// Recalculate the quotient and remainder if remainder is negative number
// And lpm_remainderpositive = true.
If (sign_r) & (lpm_remainderpositive = "true "))
Begin
Tmp_quotient = tmp_quotient + (sign_d = 1 'b1 )? 1:-1 );
Tmp_remain = tmp_remain + t_denom;
End
End

Always @ (posedge I _clock or posedge I _aclr)
Begin
If (I _aclr)
Begin
For (I = 0; I <= (lpm_pipeline + 1); I = I + 1)
Begin
Quotient_pipe [I] <={ lpm_widthn {1 'b0 }};
Remain_pipe [I] <={ lpm_widthd {1 'b0 }};
End
Pipe_ptr <= 0;
End
Else if (I _clken)
Begin
Quotient_pipe [pipe_ptr] <= tmp_quotient;
Remain_pipe [pipe_ptr] <= tmp_remain;

If (lpm_pipeline> 1)
Pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
End
End

// Continous assignment
Assign quotient = (lpm_pipeline> 0 )? Quotient_pipe [pipe_ptr]: tmp_quotient;
Assign remain = (lpm_pipeline> 0 )? Remain_pipe [pipe_ptr]: tmp_remain;

Endmodule // lpm_divide
// End of Module