< to >verilog HDL in constant declaration

1 , grammar
Statement:
parameter xx = yy;
' Define XX YY

Use:
Xx
' XX

2 , Scope
Parameter the file that acts on the Declaration, ' define reads from the compiler until the end of the compilation is valid, or the ' undef command invalidates it.

If you want parameter or ' define to work on the entire project, you can write the following declaration in a separate file and use ' include to have each file contain a declaration file:
' Ifndef XX
' Define XX yy//or parameter xx = yy;
' EndIf

' Define can also be written at the top of the file that the compiler compiles first. The compiler can usually define the compilation order or start compiling from the bottommost module. So write it down at the bottom.

3 , Role
The parameter can be used as a parameter pass at the time of the instantiate. The specific method is described in the article "parameter passing at Verilog"

Digital Declaration

There are two types of life in the Verilog: A number indicating the number of digits and a number that does not specify the number of digits

indicates the number representation of the number of digits :<size> ' <base format><number>

The size is used to indicate the digit width, which can only be expressed in decimal integers

Base format includes decimal (' d or ' d), binary (' B ' or ' B '), octal (' O ' or ' o '), hexadecimal (' H ' or ' H ')

For example

4 ' b1111//4-bit 2 decimal

' H3ac

Note that this is not a 12-bit 16 binary number, indicating that the 12-bit binary display is a 16-digit binary

Example

Parameter Lineperiod =12 ' d1040;

Parameter h_syncpulse=8 ' d120;

Parameter h_backporch=10 ' d1040;

Parameter h_activepix=706;

After synthesis (synthesize)

Lineperiod = "010000010000"

H_syncpulse = "01111000"

H_backporch = "0000010000"

H_activepix = "00000000000000000000001011000010"

You can see that the "D" is not a 12-bit decimal, but a 12-bit binary. If there are no qualifying digits, the ISE is combined by default to 32 bits, so do not exceed 32 bits when compiling Verilog.

If you limit the extra 32 digits, you will get an error when synthesizing.

Such as

Parameter h_activepix=33 ' b706;

will be error, error message is as follows:

ERROR: Hdlcompilers:34- "VGA_800X600.V" line, illegal digit (s) in binary constant ' 706 '

Also note that a problem is that Lineperiod and H_backporch are both 1040 (decimal), 10,402 binary is 11 bits (2 10 is 1024), but "h_backporch" not because the number of digits is not enough error, but the high-level cut off , it becomes "0000010000", so pay attention to the assignment problem when Verilog programming.

The default is 32 bits, which is a waste of register resources.

When the number of bits is less than the number of constants, the assignment is incorrect.

So the number of bits to be assigned has to be rich but not too wasteful of register resources .

< to >verilog HDL in constant declaration