< turn >VERILOG HDL macro definition Define

Macro definition ' Define

Represents a string with a specified identifier (that is, the name), which is in its general form:

' Define identifier (macro name) string (macro content)

such as: ' Define signal string

Its function is to specify the identifier signal instead of string, in the process of compiling preprocessing, all the signal after the command is replaced by string. This method allows the user to replace a long string with a simple name, or a meaningful name instead of a meaningless number and symbol, so that the identifier (name) is called the "macro name", and the process of replacing the macro name with a string when compiling preprocessing is called "macro expansion". ' Define is a macro definition command.

[Example 1]: ' Define Wordsize 8

Module

Reg[1: ' wordsize] data; This is equivalent to defining reg[1:8] data;

A eight-point description of the macro definition:

1) The macro name can be expressed in uppercase letters or in lowercase letters. It is recommended to use uppercase letters to distinguish them from variable names.

2) The ' Define command can appear inside the module definition, or it can appear outside the module definition. The valid range for the macro name is the end of the original file after the definition command. Usually, the ' Define command is written outside the module definition and is valid as part of the program in this program.

3) when referencing a defined macro name, you must precede the macro name with the symbol "'", which indicates that the name is a macro-defined name.

4) Use a macro name instead of a string to reduce the amount of repetitive writing of certain strings in your program. and remembering a macro name is easier than remembering an irregular string, so you know what it means when you read a program, and when you need to change a variable, you can change only the ' Define ' command line, which changes completely. In Example 1, the first definition of wordsize represents a constant of 8, when the register data is a 8-bit register. If you need to change the size of the register, simply change the command line to: ' Define Wordsize 16. The register data becomes a 16-bit register. Thus, the use of macro definitions can improve the portability and readability of the program.

5) macro definition is to replace a string with a macro name, that is, to make a simple permutation, not a grammar check. Pre-processing is still the same, regardless of the meaning is correct. The error only occurs when compiling a source program that has been expanded by the macro.

6) macro definition is not Verilog HDL statement, do not need to add semicolons at the end of the line. If a semicolon is added, it will be replaced with a semicolon . such as:

[Example 2]:module test;

Reg A, B, C, D, E, out;

' Define expression a+b+c+d;

Assign out = ' expression + E;

...

Endmodule

After the macro is expanded, the statement is:

Assign out = A+b+c+d;+e;

There is a clear syntax error.

7) When you make a macro definition, you can refer to the defined macro name, which can be replaced by layers. Such as:

[Example 3]:module test;

Reg A, B, C;

Wire out;

' Define AA A + b

' Define CC C + ' AA

Assign out = ' cc;

Endmodule

After the macro is expanded, the Assign statement is

Assign out = C + A + B;

8) The macro name and the macro content must be declared on the same line. If a comment line is included in the macro content, the Comment line does not act as the replaced content. Such as:

[Example 4]: module

' Define Typ_nand NAND #5//define a NAND with typical delay

' Typ_nand g121 (q21,n10,n11);

.........

Endmodule

After the macro is expanded, the statement is:

NAND #5 g121 (Q21,N10,N11);

The macro content can be a space, in which case the macro content is defined as empty. When the macro name is referenced, no content is replaced.

Note: The string that makes up the macro content cannot be separated by the following statement tokens.

• Comment Lines
• Digital
• String
• Confirmation character
• Keywords
• Binocular and three mesh character operators

The following macro definition declarations and references are illegal.

' Define First_half ' start of string

$display (' First_half end of string ');

Note When you use macro definitions, be aware of the following:

1) for some EDA software, when writing the source program, such as the use and preprocessing command name of the same macro name will conflict, it is recommended not to use and preprocessing the command name of the same macro name.

2) The macro name can be an ordinary identifier (variable name). For example the meaning of Signal_name and ' signal_name is different. However, this is confusing and it is recommended not to use it.

< turn >VERILOG HDL macro definition Define