FPGA, the general external crystal oscillator is 50Mhz, if a module in the circuit needs a 25mhz clock, then a 2-way, this is quite easy, the following is a method, and can be implemented with a binary counter. The code is not written here. Easy. The same principle, the four crossover is also very simple. Process (CLK)--clk input clock;
Begin
if (rst = ' 0 ') then--rst reset signal;
Clkout <= ' 0 ';
elsif (clk;event and CLK = ' 1 ') then
Clkout <= not CLK;
End If;
End process;
But what if we achieve a three-way divide?? Isn't it3The dividers should be each1.5OfClockOn0Change1、1Change0, but the question came, where did it come from1.5Aclock?The counter does not produce1.5!!The interval between the positive and negative source triggers is exactly0.5Aclock?So we have two of them.Clock, one isPosedge CLK, one isNegedge CLK, and the last one will be twoClockDoor, so that it can produce a0.5AClockThe The following code is given:::
Library IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_arith.all;
Use Ieee.std_logic_unsigned.all;
Entity Clk_div_n is
Port (Clk:in std_logic;
Rst:in std_logic;
Clkout:out Std_logic
);
End Clk_div_n;
Architecture RTL of Clk_div_n is
Constant N:integer range 0 to 10: = 6; --Here The n can be any value, of course greater than 1.
Signal clk_p:std_logic;
Signal clk_n:std_logic;
Signal Cnt_p:integer range 0 to N;
Signal Cnt_n:integer range 0 to N;
Begin
Process (clk_p, clk_n)
Begin
if ((n mod 2) = 0) Then
Clkout <= clk_p;
Else
Clkout <= clk_p or clk_n;
End If;
End process;
Process (CLK, RST)
Begin
if (rst = ' 0 ') then
Cnt_p <= 0;
elsif (CLK ' event and CLK = ' 1 ') then
if (cnt_p = n-1) Then
Cnt_p <= 0;
Else
Cnt_p <= cnt_p + 1;
End If;
End If;
End process;
Process (CLK, RST)
Begin
if (rst = ' 0 ') then
Clk_p <= ' 0 ';
elsif (CLK ' event and CLK = ' 1 ') then
if (Cnt_p < (N/2)) Then
Clk_p <= ' 1 ';
Else
Clk_p <= ' 0 ';
End If;
End If;
End process;
Process (CLK, RST)
Begin
if (rst = ' 0 ') then
Cnt_n <= 0;
elsif (CLK ' event and CLK = ' 0 ') then
if (cnt_n = n-1) Then
Cnt_n <= 0;
Else
Cnt_n <= cnt_n + 1;
End If;
End If;
End process;
Process (CLK, RST)
Begin
if (rst = ' 0 ') then
Clk_n <= ' 0 ';
elsif (CLK ' event and CLK = ' 0 ') then
if (Cnt_n < (N/2)) Then
Clk_n <= ' 1 ';
Else
Clk_n <= ' 0 ';
End If;
End If;
End process;
End RTL;
Next I give the corresponding Testbench:: Interested can use make a simulation in Modelsim
LIBRARY IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_arith.all;
Use Ieee.std_logic_unsigned.all;
ENTITY CLK_DIV_N_TB is
END CLK_DIV_N_TB;
ARCHITECTURE Clk_div_tb_arch of CLK_DIV_N_TB is
SIGNAL clkout:std_logic;
SIGNAL rst:std_logic: = ' 0 ';
SIGNAL clk:std_logic: = ' 1 ';
COMPONENT Clk_div_n
PORT (
Clk:in std_logic;
Rst:in std_logic;
Clkout:out Std_logic
);
END COMPONENT;
BEGIN
Process
Begin
Wait for 50ns;
CLK <= not CLK;
End process;
RST <= ' 1 ' after 200ns;
Test:clk_div_n
PORT MAP (
CLK = CLK,
RST = rst,
Clkout = clkout);
END Clk_div_tb_arch;
From for notes (Wiz)
An arbitrary integer divider for VHDL language implementation
