An in-depth understanding of I2C bus clock synchronization and bus arbitration

An in-depth understanding of I2C bus clock synchronization and bus arbitration

Each IIC bus device has the same circuit structure of the SDA and SCL pins, and the output drive of the pins is connected with the input buffer. The output is a field effect tube with an open drain path, and the input buffer is a high-input impedance phase generator [1]. This type of circuit has two features:

① Because SDA and SCL are Drain open circuit structures, the "line and" logic of signals are implemented by means of external pull-up resistance;

② At the same time as the output signal, the pin level is also checked to check whether it is consistent with the output just now. Provides hardware infrastructure for "Clock Synchronization" and "bus arbitration.

Internal Structure of I2C bus interface

The IIC device only operates on the bus by "grounding the line"-the output logic is 0. Based on the IIC bus design, there is no possibility of level conflict on the line. If one device sends logic 0 and the other sends logic 1, only logic 0 is displayed on the line. That is to say, if a level conflict occurs, the sending logic 0 is always the "Winner ". The physical connection of the bus allows the master device to read data from colleagues who write data to the bus. In this way, when the two main devices compete for the bus, the "Winner" does not know the competition. Only the "loser" finds the conflict. When a logic 1 is written, the system reads 0, and then exits from the competition. Clock Synchronization

If the Controller wants the master controller to reduce the transmission speed, it can notify the master controller by actively reducing the SCL and extending its low-level time, when the main controller prepares for the next transfer, it waits until it finds that the SCL level is lowered until the Controller completes the operation and releases the Control of the SCL line. In this way, the master controller is actually controlled by the clock synchronization of the controller. It can be seen that the low level of the online SCL is determined by the device with the longest clock low level, and the high level time is determined by the device with the lowest high level time. This is clock synchronization, which solves the speed synchronization of I2C bus.

Bus Arbitration

Assume that the data to be sent by the master controller 1 is "101 ......"; The data data2 to be sent by master controller 2 is "1001 ......" After the bus is started, the two master controllers must detect their output levels every time they send a data bit. As long as the detection level is consistent with the level they send, they will continue to occupy the bus. In this case, the bus still cannot be arbitrated. When master controller 1 sends 3rd-Bit Data "1" (master controller 2 sends "0"), the SDA level is "0" due to the "line and" result ", in this way, when the master controller 1 detects its own output power, it will detect a "0" level that does not match itself. In this case, master controller 1 had to give up control of the bus, so master controller 2 became the only master of the bus.
It is not difficult to see:

• ① No data will be lost for master controller 1 and master controller 2 throughout the arbitration process;
• ② Each master controller has no prior control over the bus;
• ③ Bus control is then determined. They follow the "low level first" principle, that is, whoever sends the low level first will have control over the bus.

According to the above description, the following rules can be summarized in "Clock Synchronization" and "bus arbitration:

• ① The master controller adjusts the speed synchronization problem with the slave device by detecting the level on the SCL-clock synchronization;
• ② The main controller checks the level sent by SDA to determine whether a "Conflict" of the bus-bus arbitration has occurred. Therefore, the "Clock Synchronization" and "bus arbitration" of I2C bus are achieved by the special structure of the device's own interface.

[1] Same phase generator: when the input is high, the output is also high. When the input is low, the output is also low. It is mainly used in scenarios where buffering is required, that is, as long as a small amount of current is input, a large amount of current can be output to increase the load carrying capacity.