Analysis and research of RTOS multi-kernel expansion based on multi-core processor five

4.4 SMP-enabled interrupt module design in SMP environment if all external interrupts are handled by one CPU, the interrupt response time of SMP system is still the level of single core processor. So the SMP hardware platform is either binding the interrupt to the specified CPU, or not binding to the specified CPU. If the interrupt is not bound to the specified CPU, you need to select one to handle the interrupt request in a CPU that does not mask the interrupt, and how the X86 platform's IO APIC has this capability;