Analysis and Simulation of VGA ipcore with OpenRisc-27-wishbone Interface

Introduction

Graphics always give people an intuitive feeling. It makes sense to make orpsoc output of image/video, while VGA is a good choice.

This section analyzes the VGA module of the next wishbone interface.

1. Module preparation

Download:

Http://opencores.org/project,vga_ LCD

2. Module Architecture

3. Use of modules

This step requires a bit of LCD/vedio-related knowledge. I have written a Linux driver for lcdc and have experience in digital TV development, so it is much easier to understand.

Here we only use the most important timing. For more information, see spec.

The figure below should be carefully read and understood. After understanding, many things will be explained later.

Suggestion: Imagine the TV refresh process.

This module is relatively simple and does not have complex image processing functions. However, the following concepts must be understood:

1> row synchronization (horizontal synchronization), row width, front shoulder, and back shoulder.

2> column synchronization (vertical synchronization) and field width

3> Scanning

4> pixels

5> RGB

6> grayscale

7> wishbone's burst access

8> dual BUFFER MECHANISM

9> alpha blanking

10> FIFO underrun and overrun

11> essential functions of the palette

4. Overall simulation structure

To simulate the vga_eng_top module, you need to establish the necessary simulation models and connect them.

5. simulation process overview

1> Reset

2> test whether there is a problem with reading and writing the Register (reg_test)

3> initialize mem.

4> test whether the output sequence in all VGA modes is correct (tim_test). There are 6 Modes in total.

5> test the data correctness of DVI pixel: dvi_pd_test

6> test the data correctness of VGA pixel: pd1_test

7> test the FIFO underrun: ur_test

6. parameter settings in each mode:

 

For (mode = 0; mode <6; mode = mode + 1) Begin // reset corescen = 0; m0.wb _ wr1 ('ctrl, 4' HF, 32 'h0000 _ 0000); repeat (10) @ (posedge CLK); $ display ("Mode: % 0d", mode); Case (mode) 0: beginthsync = 0; thgdel = 0; thgate = 319; // gate = 320 thlen = 345; tvsync = 0; tvgdel = 0; tvgate = 239; // vgate = 240 tvlen = 245; hpol = 0; vpol = 0; cpol = 0; bpol = 0; end1: beginthsync = 18; thgdel = 18; thgate = 319; // gate = 320 thlen = 390; tvsync = 18; tvgdel = 18; tvgate = 239; // vgate = 240 tvlen = 290; hpol = 1; vpol = 0; cpol = 0; bpol = 0; end2: beginthsync = 1; thgdel = 1; thgate = 639; // hgate = 640 thlen = 644; tvsync = 1; tvgdel = 1; tvgate = 479; // vgate = 480 tvlen = 484; hpol = 0; vpol = 1; cpol = 0; bpol = 0; end3: beginthsync = 0; thgdel = 2; thgate = 799; // hgate = 800 thlen = 804; tvsync = 0; tvgdel = 2; tvgate = 599; // vgate = 600 tvlen = 604; hpol = 0; vpol = 0; cpol = 1; bpol = 0; end4: beginthsync = 3; thgdel = 2; thgate = 799; // hgate = 800 thlen = 807; tvsync = 2; tvgdel = 2; tvgate = 599; // vgate = 600 tvlen = 606; hpol = 0; vpol = 0; cpol = 0; bpol = 1; end5: beginthsync = 6; thgdel = 2; thgate = 799; // hgate = 800 thlen = 810; tvsync = 4; tvgdel = 2; tvgate = 599; // vgate = 600 tvlen = 608; hpol = 1; vpol = 1; cpol = 1; bpol = 1; endendcase/* thsync = 0; thgdel = 0; thgate = 64; thlen = 70; tvsync = 0; tvgdel = 0; tvgate = 64; tvlen = 70; hpol = 0; vpol = 0; cpol = 0; bpol = 0; */m0.wb _ wr1 ('htim, 4' HF, {thsync, thgdel, thgate}); m0.wb _ wr1 ('vtim, 4' HF, {tvsync, tvgdel, tvgate}); m0.wb _ wr1 ('hvlen, 4' HF, {thlen, tvlen}); m0.wb _ wr1 ('ctrl, 4' HF, {16 'h0, bpol, cpol, vpol, hpol, 1' B0, // pc2' H0, // CD2 'h0, // vbl2' H0, // reserved5' h01 // bank switch, Int, videoen}); repeat (2) @ (posedge vsync ); SCEN = 1; repeat (4) @ (posedge vsync); End

 

7. Simulation results

Note: The simulation process takes a long time (my computer has more than 30 mins). Therefore, only the output waveform of one line of data is selected, as shown below;

We can see the timing relationships of the line Synchronization Model, mixed synchronization signal, blank signal, RGB signal, and other important signals.

8. Summary

The rest of the work is FPGA verification. refer to the previous Blog content and link it to arbiter_detail.

Like the interface of the previously FFT module, it is also a slave interface and a master interface.

Http://blog.csdn.net/rill_zhen/article/details/8849149

Appendix:

I have uploaded all the source code and documents for this experiment:

Http://download.csdn.net/detail/rill_zhen/5353755

Good luck!