Analysis of arm B and BL instruction

B or BL directives cause the processor to move to the "subroutine name" to begin execution. The difference between the two is that the BL instruction is transferred to the child

Copy the address of the next instruction to R14 (LR, link register) before executing the program. Because the BL directive preserves the ground of the next instruction

Address, so using the directive "MOV PC, LR" can be implemented subroutine return. and the B instruction is unable to implement the subroutine return, can only real

is a simple jump. When the user is programming, can choose the appropriate subroutine to call the statement according to the concrete application.

Area Init,code,readonly

The pseudo directive defines a code snippet, the segment name is init, and the property is read-only
ENTRY The entry point identification of the program

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BL delay; Call delay

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MOV pc,lr; back

The following in the blog to see the thought of speaking more details on the cuff over

Some summaries of ARM assembly instructions
ARM assembly instructions are many, but the real use is not a lot, but also need to seriously think about less.
The more useful is MOV B BL LDR STR
or through the specific assembly code to learn it.
@ Disable Watch Dog timer
mov r1, #0x53000000//Instant number addressing mode
mov R2, #0x0
STR R2, [R1]
Immediately number addressing, the immediate number requires "#" as the prefix, for hexadecimal number, but also after the # plus 0x or &. STR is

The more important instruction, corresponds to it is LDR. The arm instruction set is loaded/stored, which means it is only processed in registers

Data. Then the access to system memory is often used for STR and LDR. STR is the data transfer on the register to the specified address

The memory. It's the format I personally think is very special:
STR (condition) source register,< memory address >
For example, STR R0, [R1], means r0-> [R1], which writes the source registers in front of them, as opposed to MOV and LDR.
LDR should be very common. LDR is the transfer of data from memory to registers. And there's a pseudo directive that's also LDR, so I have

A question that cannot be solved. Look at this code:
mov r1, #GPIO_CTL_BASE
Add R1, R1, #oGPIO_F
LDR R2,=0X55AA//0X55AA is an immediate number Ah, the front plus a = what to do.
For the ldr of the sentence, I do not understand, if you take = removed, is not compiled. I looked up some information, a personal feeling.

Aware of the reason: this = should indicate that LDR is not arm instruction, but pseudo instruction. As a pseudo instruction, the LDR format is as follows:
LDR registers, = Numeric constants/label
Its role is to transfer a 32-bit address or a constant into the register. Ho-ho, that people might ask,
"MOV R2, #0x55aa" can also ah. That should be the case. However, LDR is a pseudo directive, which means that compile-time compilers will handle

It's. How to deal with it. The rules are as follows: If the numeric constant is within the MOV instruction range, the assembler will take this instruction as the Mov

。 If it is not in the Mov range, the assembler puts the constant behind the program, reads it with LDR, and the PC and the constant cannot be offset more than

4KB.
Then say the jump instructions. ARM has two ways to jump.
(1) MOV pc < jump address
This to the program counter PC directly write the jump address, can be in 4GB continuous space any jump.
(2) through B BL BLX BX can be completed in the current instruction forward or back 32MB address space jump (why 32MB it.

The register is 32-bit, at which point the value is 24-bit signed, so 32MB).
B is the simplest jump instruction. Note that the actual value of the jump instruction is not an absolute address, but a relative address--is relative to the current

An offset of the value of the PC, which is computed by the assembler.
BL is very often used. It saves the current contents of the PC in register LR (R14) before jumping. The classic use of BL is as follows:
BL NEXT; Jump to Next
......
NEXT
......
mov pc, LR; Returns from a subroutine.
Finally, mention the thumb instructions. The ARM architecture also supports a 16-bit thumb instruction set. The thumb instruction set is a subset of the arm instruction set, which

Retains the 32-bit code advantage while also greatly saving storage space. Since the thumb instruction set is only 16 bits long, its instructions

Quite a lot. It and arm each have their own application occasions. For system performance, we should use 32-bit storage system and arm instruction set.

For system costs and power consumption requirements, should use 16-bit storage system and arm instruction set.
The understanding of ARM anomaly (exceptions)
Category: Technical notes
Bi Set Notes
1. The understanding of ARM anomaly (exceptions)
All of the system bootstrapper will have a similar code in front of it, as follows:
. globl _start; system Reset Position
_start:b reset; jump codes corresponding to each exception vector
Ldr pc, _undefined_instruction; undefined instruction exception
LDR pc, _software_interrupt software interrupt exception
Ldr pc, _prefetch_abort, memory operation exception
LDR pc, _data_abort data exception
Ldr pc, _not_used; not used
Ldr pc, _IRQ, slow interrupt exception
Ldr pc, _fiq, fast interrupt exception

From this we can see that ARM supports 7 kinds of exceptions. How does arm respond when an exception occurs? The first reset is exceptionally good.

Understand that it is placed in the 0x0 position, executes it as soon as it is on, and our program is always executed from the reset exception handler because

This reset exception handler does not need to be returned. So how do you perform to the following exception handlers?
After reading the book, understand the arm of the exception response process, so can answer the previous question.
When an exception occurs, ARM automatically performs the following steps:
(1) Place the address of the next instruction in the connection register LR (usually R14) so that it can be handled from the correct position when handling the exception return

Continue execution.
(2) Copy the corresponding CPSR (the current program status register) to the SPSR (the Backup program status register). When exiting from an exception

, it can be restored by SPSR to CPSR.
(3) According to the type of exception, the CPSR is forced to set the running mode bit.
(4) Forcing the PC (program counter) to remove the next instruction from the relevant exception vector address, and thus jump to the corresponding exception handler

In order.
I did not delve into what these types of anomalies represented. Because the usual care about reset, there is no need to find out.
ARM sets the address of the anomaly vector:
b Reset; reset 0x0
Ldr pc, _undefined_instruction, undefined instruction exception 0x4
LDR pc, _software_interrupt software interrupt exception 0x8
Ldr pc, _prefetch_abort, prefetch command 0xc
LDR pc, _data_abort data 0x10
LDR pc, _not_used not used 0x14
Ldr pc, _IRQ, slow interrupt exception 0x18
Ldr pc, _fiq, fast interrupt exception 0x1c
This is a very simple way to understand this piece of code. When an exception is encountered, the PC is forced to set the corresponding exception vector, which jumps to the corresponding

Handler, and then return to the main program to continue execution.
The interrupt vectors for these bootstrapper are for the bootstrapper to use only, and once the bootstrapper has booted the Linux kernel, it will use

its own interrupt vector.
Ho-ho, that's a problem again. For example, when arm interrupts (IRQ), it always runs to the 0x18 to execute AH. How does the Linux kernel

You can use your interrupt vector. The reason is that the Linux kernel uses page storage management. After opening the MMU page map, the CPU

The address that is emitted is the virtual address, not the physical address. In the case of the Linux kernel, the virtual address 0x18 after mapping the physical address

Is 0xc000 0018. So Linux puts the interrupt vector on the 0xc000 0018.
Two main functions of the MMU:
(1) Security: Specify access rights
(2) Provide address space: The discontinuous space is converted to continuous.
The 2nd is to realize the meaning of the page-type storage.

. globl _start; system Reset Position
_start:b reset; jump codes corresponding to each exception vector
Ldr pc, _undefined_instruction; undefined instruction exception

......

_undefined_instruction:
. Word undefined_instruction

Perhaps some people will have the question, also is the jump instruction, why the first sentence uses is B reset;
And a few of the following are used Ldr.

To understand this problem, we take an undefined instruction exception as an example.

When this exception occurs, the CPU always jumps to 0x4, which is the virtual address and which physical address it maps to.
Depends on the specific mapping.
Ldr pc, _undefined_instruction
Relative addressing, jump to the label _undefined_instruction, but the real jump address is actually _undefined_instruction

Content is--undefined_instruction. The word is equivalent to:
_undefined_instruction DW Undefined_instruction (see note 3).
This address undefined_instruction in the end how far it is hard to say, perhaps with the label _undefined_instruction in the same

Page, perhaps in a very far place. However, except reset, the other exception is MMU began to work before it can happen, so

Undefined_instruction's address has also been mapped by MMU.
When the new power is added, the CPU begins to execute from the 0x0, the MMU has not yet started to work, at this time the virtual address and physical address are the same; the other side

, the reboot may occur after the MMU starts work, if reset also use LDR have a problem, because this time virtual address and physical

The address is completely different.

Therefore, the reason why reset with B, is because reset in the MMU before and after the establishment of the possibility, and other anomalies only in MMU established

Before it happens. With b Reset,reset subroutine and reset vector on the same page, so there will be no problem (b is relative to jump)

。 If the two are too far apart, the compiler will complain