Analysis of the implementation principle of nandflash device driven bottom based on MTD (VII.)

Reprint Address: http://blog.csdn.net/eilianlau/article/details/6966284

After initializing the basic hardware configuration, the probe function will begin interacting with the NAND chip, which is mainly about the following aspects: Reading the ID of the NAND chip, and then checking the table to get the NAND chip such as the manufacturer, page size,erase size and chip Size, and then, depending on the value of the options in the struct nand_chip, either look for the bad block table in a specific position in the NAND chip, or scan the entire NAND chip and create a bad block table in memory. These are done by Nand_scan ().

The Nand_scan function consists of two two functions, namely the Nand_scan_ident function and the Nand_scan_tail function. Where the Nand_scan_ident function reads the ID of the NAND chip, and the Nand_scan_tail function finds or establishes the BBT (bad block table).
The Last Call Add_mtd_partitions () adds the partition table defined in the platform file.

D nand_chip initialization, about nand_chip on the 5th part of the article has been introduced

/** initialization nand_chip Structure **/
static void S3c2410_nand_init_chip (struct s3c2410_nand_info *info,
struct S3C2410_NAND_MTD *NMTD,
struct S3c2410_nand_set *set)
{
struct Nand_chip *chip = &nmtd->chip;//&nmtd->chip=& (nmtd->chip)
void __iomem *regs = info->regs;//used to save an address.
/** The following section is assigning values to function pointers in Nand_chip **/
Chip->write_buf = S3c2410_nand_write_buf;
Chip->read_buf = S3c2410_nand_read_buf;
Chip->select_chip = s3c2410_nand_select_chip;
Chip->chip_delay = 50;//delay Time
Chip->priv = NMTD; This is very important. Assign struct S3C2410_NAND_MTD to private data members of Nand_chip
Chip->options = 0;//in the 5th article this place seems to be wrong, maybe there will be an assignment, because no 0 defines this macro
Chip->controller = &info->controller;//pointer to struct NAND_HW_CONTROL
。。。。。。。。。。。。。。。。
Case TYPE_S3C2440:
Chip->io_addr_w = regs + S3c2440_nfdata;//2440nand Data Registers
Info->sel_reg = regs + S3c2440_nfcont;//2440nand Control Registers
Info->sel_bit = s3c2440_nfcont_nfce;//1<<1, now chip selection signal for disable, the default is disable
Chip->cmd_ctrl = s3c2440_nand_hwcontrol;//Control ale/cle/nce, also used to write commands and addresses
Chip->dev_ready = s3c2440_nand_devready;//Device Ready
CHIP-&GT;READ_BUF = s3c2440_nand_read_buf;//reads the data in the chip into the buffer
Chip->write_buf = s3c2440_nand_write_buf;//writes data from the buffer to the chip
Break

。。。。。。。。。。。。。。。。
}

Chip->io_addr_r = chip->io_addr_w;

Nmtd->info = info;
Nmtd->mtd.priv = chip; The pointer to the struct NAND_CHIP structure is assigned to the PRIV member variable of the struct mtd_info, because calls between many functions in the MTD core pass only struct mtd_info, It needs to get struct nand_chip by PRIV member variables.
Nmtd->mtd.owner = This_module;
Nmtd->set = set;
/** If you use hardware ecc**/
if (HARDWARE_ECC) {
Chip->ecc.calculate = S3C2410_NAND_CALCULATE_ECC;
Chip->ecc.correct = S3c2410_nand_correct_data;
Chip->ecc.mode = NAND_ECC_HW;
Switch (info->cpu_type) {
。。。。。。。。。。。。。。。。
Case TYPE_S3C2440:
Chip->ecc.hwctl = S3C2440_NAND_ENABLE_HWECC;
Chip->ecc.calculate = S3C2440_NAND_CALCULATE_ECC;
Break
}
} else {

Using Software checksums

Chip->ecc.mode = Nand_ecc_soft;
}
/**ecc*/
if (set->ecc_layout!= NULL)
Chip->ecc.layout = set->ecc_layout;
/** forbid ecc*/
if (SET-&GT;DISABLE_ECC)
Chip->ecc.mode = Nand_ecc_none;

Switch (chip->ecc.mode) {
。。。。。。。。。。。
}

/* If You use u-boot BBT creation code, specifying this flag would
* Let the kernel fish out of the BBT from the NAND, and also skip the
* Full NAND Scan which can take 1/2s or so. Little things ... *
if (SET-&GT;FLASH_BBT)//When flashbbt=1 the system will skip scanning BBT when it is started
Chip->options |= NAND_USE_FLASH_BBT | Nand_skip_bbtscan;
}

Next is to read the ID of the chip call int nand_scan_ident (struct mtd_info *mtd, int maxchips) function This function is generic, defined in the NAND_BASE.C has not been studied for a while

id**/of/** reading chip
Nmtd->scan_res = Nand_scan_ident (&NMTD->MTD,
(sets)? SETS->NR_CHIPS:1);

if (Nmtd->scan_res = = 0) {/** returns 0**/if Read succeeds
S3c2410_nand_update_chip (info, NMTD);/update, take a look at its prototype
Nand_scan_tail (&NMTD->MTD);/Find or Create BBT (bad block table)
S3c2410_nand_add_partition (info, NMTD, sets);//add partition, related to board-level file

The implementation of this function must be called Add_mtd_device (&MTD->MTD) ...

}

e) s3c2410_nand_update_chip (struct S3c2410_nand_info *info,
struct S3C2410_NAND_MTD *NMTD) analysis

static void S3c2410_nand_update_chip (struct s3c2410_nand_info *info,
struct S3C2410_NAND_MTD *NMTD)
{
struct Nand_chip *chip = &nmtd->chip;

dev_dbg (Info->device, "Chip%p => page Shift%d\n",
Chip, Chip->page_shift);

if (Chip->ecc.mode!= NAND_ECC_HW)//If not hardware checksum is returned directly
Return

/* Change the behaviour depending on wether we are using
* The large or small page NAND device * *

if (Chip->page_shift > a) {//page_shift a large page with a bit to indicate the size of the page larger than 2KB
Chip->ecc.size = 256;
Chip->ecc.bytes = 3;
} else {Small page
Chip->ecc.size = 512;
Chip->ecc.bytes = 3;
Chip->ecc.layout = &nand_hw_eccoob;
}

For these ecc_layout of the temporary still don't understand ...

}

Look at the Nand_hw_eccoob. It is a structure used to manage ECC and bad blocks in OOB (the 5th article has detailed instructions)

static struct Nand_ecclayout Nand_hw_eccoob = {
. eccbytes = 3,
. Eccpos = {0, 1, 2},//ecc position in OOB
. Oobfree = {8, 8}}//free OOB byte region
};

*******************

When the nand_chip is initialized above, there is a nand_chip (struct NAND_ECC_CTRL) structure inside it. There are a number of member functions that are assigned values in the initialization process Nand_ There are also a number of member functions assigned values in the chip ... As for how they are implemented, look back to see their implementation. It's not very difficult ...