Analysis on SPI bus controller of STC Single Chip Microcomputer

In the slave mode, the speed cannot be too fast. It is better to use sysclk/8 or less, with a write conflict and completion mark.

 

For the SPI bus of the SD card, the SPI of the SD card is the input lock of the rising edge of the CLK when reading data, and the output data is also on the rising edge. Then, the corresponding cpol is 1 (high in idle time), cpha is 1 (saved in the rising edge), and DORD is 0 (MSB first ).

The SPI data register is spdat.

 

The core of SPI is the 8-displacement register and the input data buffer. data can be sent and received at the same time. During SPI transmission, the sent and received data is stored in an 8-bit data buffer.

In master mode, only one byte of data needs to be sent to spdat. In slave mode, data transmission starts only when/SS is low and receives the appropriate clock signal (naturally, the host can send the clock signal. In the mode, after receiving 1 byte/SS, it changes to a high level. The hardware logic flag spif indicates that the receiving is complete, waiting for receiving the next byte.

Sclk is output in master mode and input in slave mode.

Transmission process: Transmission always starts from the host. The 8-shift register of the host is moved into the 8-shift register of the slave, at the same time, the 8-shift register of the host is moved into the 8-shift register of the host, that is, sending and receiving are completed at the same time. When the transmission is completed in 1 byte, The spif is set and the sclk signal is stopped.