Analysis on the NAND Flash Driver of S3C2410

Analysis on the NAND Flash Driver of S3C2410

In the past, I used to directly use the code written by others without worrying about how to implement it. Last night, I compared Samsung 2410 and K The 9f1208 chip reads the code and finally understands how to implement the NAND Flash operation step by step. The following code can be used to operate a NAND flash in Vivi or kernel. In general, it can be divided into four steps: 1. Select the NAND device 2. send command to NAND device 3. Operation 4. de-select the NAND device. The implementation code of the above four steps is as follows: 1. Select the NAND device # define nand_select () This-> hwcontrol (nand_ctl_setnce);/nand_command (MTD, nand_cmd_reset,-1,-1);/udelay (10 ); hwcontrol (nand_ctl_setnce) is used to set the nand flash memory chip of the 2410 NAND Flash configuration (nfconf) Register. The enable bit is 0. For more information, see Samsung 2410 datasheet. Nand flash memory chip enable [11] nand flash memory nfce control0: NAND Flash nfce = L (active) 1: NAND Flash nfce = H (inactive) (after auto-boot, nfce will be inactive .) nand_command (MTD, nand_assist_reset,-1,-1); the literal meaning is reset NAND device. For details, see the following. 2. send command to NAND device this step mainly involves the following processes 1. Begin command latch cycle implementation code: This-> hwcontrol (nand_ctl_setcle ); // set command latch enablethis-> hwcontrol (nand_ctl_dat_out); // I do not know this yet. 2. write out the command to the device implementation code: This-> write_cmd (command ); // write the command to NAND Flash command set (nfcmd) register3, set ale and clear CLE to start address cycle implementation code: This-> hwcontrol (nand_ctl_clrcle );// Clear the command latch enable this-> hwcontrol (nand_ctl_setale); // set the address latch enable4, serially input address implementation code: This-> write_addr (Address ); // write the address to NAND flash Address set (nfaddr) Register. For details, refer to the NAND Flash Datasheet and the addressing mode of nand flash [http://sniper167.bokee.com/5494041.html#5, latch in address implementation code: this-> hwcontrol (nand_ctl_clrale); // clear the address latch enable t His-> hwcontrol (nand_ctl_dat_in); // I do not know this. 6. Pause? US implementation code: udelay (?) // Latency, you have to give NAND flash a response time. 3 // time depends on the specific NAND Flash. 3. Operation is mainly for NAND Flash data (nfdata) write or read data in register, for example, static u_char read_data (void) {return (u_char) nfdata;} 4. de-select the NAND device implementation code: # define nand_deselect () this-> hwcontrol (nand_ctl_clrnce); opposite to select the NAND device, the nand flash memory chip enable position of the NAND Flash configuration (nfconf) Register is 1 to this point, one operation is completed for NAND flash on the Samsung 2410 platform. The above is my personal understanding. If anything is incorrect, please point it out. Thank you. The following is a problem that I haven't figured out. If you want to see it, please give me some advice: This code is from mizi_linux/Drivers/MTD/NAND/smc_s. 3c2410. cstatic void smc_hwcontrol (INT cmd) {Switch (CMD) {Case nand_ctl_setnce: nfconf & = ~ Nfconf_nfce_high; break; case when: nfconf | = nfconf_nfce_high; break; Case nand_ctl_setcle: break; case when: break; case nand_ctl_dat_out: break;} nand_ctl_setcle, nand_ctl_clrcle, nand_ctl_setale, and the following command lines are passed in. Can this achieve set or clear?