Application of Time Division multithreading in Single Chip Microcomputer System

1-hour multi-thread structure application

Generally, various control systems used by single-chip microcomputer have various interaction processes such as field data collection, control output, working status detection, and data transmission; the mismatch between the response speed of various peripherals and MCU is an important factor restricting the overall performance of the system. In the face of this interaction bottleneck, the use of time-based multi-thread architecture can achieve good results.

Especially when the system and peripherals frequently interact with each other, the system's real-time response capability can be significantly improved. Here we use the time-cycle rotation scheduling algorithm to achieve the multi-task control goal in the single chip microcomputer system.

1.1 multi-thread implementation of the time rotation scheduling algorithm

The time-based rotation scheduling algorithm is implemented based on the CPU execution time used by multiple threads in turn. In application scenarios with frequent peripheral interactions, the CPU waits for peripheral response time consumption caused by mismatch of response speed can be effectively solved, thus improving the utilization of MCU computing components.

During multi-thread scheduling and switching, the running environment of the previous thread should be protected and the next thread should be ready. For single-chip microcomputer systems, strict real-time multi-threaded control will be subject to capacity, interrupt source, pointer and other system resources.

This paper is an application system based on c8051f005 single-chip microcomputer. It is based on the 805l kernel and does not have much space to store or protect the field data (such as program pointers, program status characters, accumulators, and so on) During task switching ), it is also difficult to apply the incentive mechanism for preemptible real-time task switching, and the MCU speed is also limited.

To address these resource bottlenecks of single-chip microcomputer, the time-cycle rotation algorithm is used as the multi-thread control algorithm architecture, and non-preemptible asynchronous processing methods are used to rationally allocate and use general working register groups, by integrating or segmenting the functional module structure, the control program is divided into various thread tasks to shorten the idle time of the CPU, and the execution time of each thread is controlled in the time slice, to reduce the complexity of context switching and reduce development risks.

1.2 multithreading management policies and applications

(1) length of time slice

Through a reasonable combination of control functions and time series, program segments divided by time slice length should ensure that the Execution Code segments of each thread are completed within the "time slice, this reduces the complexity of thread task control and design risks. For details about the implementation principles, see section 2nd.

(2) thread coordination

By setting the identification quantity, the thread tasks in each time slice are coordinated. For example, function blocks such as dejitters and key-value redundancy reading in keyboard input, sampling triggering and numerical reading in A/D data collection, and SPI data transmission, job step subdivision of task threads. By setting the number of phase identifiers of a thread, it coordinates the thread execution pace of the time slice before and after.

(3) thread management

In the clock interrupt service program, use the task number to schedule the thread execution order. Select the task number to be executed next based on the control target, device status, and execution result of the current thread. The task thread execution is completed in the main control loop program. That is to say, separating the time slice drive, task scheduling, and task thread processing is conducive to building a flexible and efficient software framework structure and improving the system's real-time response capability and maintainability.

In an application system built on the c8051f005 chip, in order to shorten the execution time of the time slice interrupt service program and improve the system's interrupt response capability, task Thread Scheduling and context switching control are implemented in the T2 clock interruption service program. The tstatechange and timeslice are used for Thread Scheduling when an event occurs. Tstatechange is used to control the direction of the main control loop, and timeslice is used to control the execution order of the scheduling ready thread.

To reduce system power consumption and improve system reliability, the MCU enters the sleep state after each cycle, the MCU is awakened by time slice T2 interruption, other asynchronous interrupt sources, or pin-triggered events. The tstatechange status identifier quantity controls the direction of the main control loop to differentiate the asynchronous interrupt events such as thread scheduling of time slice tasks and non-t2 tasks. The main control loop flow 1 shows that its thread control can be implemented using the following program structure.

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This system framework has the following advantages: it can easily build a multi-threaded architecture with parallel control relationships; the execution time of task threads is clear; it also facilitates the adjustment of task thread execution timing and maintenance function modules.

Defect: due to the non-preemptible control mode, the time-critical asynchronous events cannot be prioritized during thread scheduling, which is also an inherent defect of the kernel of the device.

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2. determine the length of the time slice

After overall consideration of the Code volume, peripheral response, system response performance, and thread Switching Data Protection Volume of the task thread segment, determine the switching unit using loms as the thread time slice. Consider the following factors:

(1) The code size of the task thread segment

Based on the size of each function module and logic relationships such as relevance and time sequence, modules are decomposed and merged to form thread Execution Code segments based on the cohesion of each function module and the amount of thread switching computing, to ensure that the thread Execution Code segment (including the execution time of the interrupted service program) can be completed in the time slice, This simplifies the control model and reduces the complexity of context switching in multithreading.

For example, if you want to process keyboard input, you can remove the jitters of keyboard input, read key values in redundancy, and enable the function of pressing and clicking keys continuously. By setting several identification variables and segmenting key value processing thread time sequence job steps, each job execution time slice is smaller than loms, so as to adapt to the time constraints of clock chip scheduling and reduce design risks.

20 ~ 30 ms anti-jitter delay. You can set the identifier quantity keydelay to count the latency in the time slice interruption service program. The following processing can be done in the main loop program.

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(2) peripheral response

Considering the latency factors of MCU interaction with various peripherals, The Impact of factors such as the peripheral Delay Time, thread switching, and time slice cycle on the overall system performance should be balanced, maximize CPU usage.

(3) A/D Data Conversion Rate

The sampling frequency of the read temperature and power values takes into account the size of the time slice according to the/D Conversion Rate on the chip of c8051f005 and the signal redundancy reading requirements of digital filtering.

3 Special notes

① Time slice interrupt t2 should be set to the highest priority to prevent other interrupt programs from interfering with the real-time processing of the time slice scheduler.

② The Scheduling Algorithm of the interrupted service program should be as short as possible to improve the system's response capability.

③ Pay attention to stack overflow control.

④ The thread code segments allocated in the time slice should be reasonably combined and scheduled to balance the CPU time slice and reduce design risks.

⑤ When initializing the system status, ensure the creation of the thread status identifier and enable T2.

6. Handle the interrupted service program execution time with caution to avoid the normal processing of the thread time slice, resulting in control disorder and system crash.