Area Structure and Power Consumption Design for advanced FPGA design architecture, implementation and optimization Learning

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• Clock offset

I. Area Structure Design

1. the folding assembly line can optimize the area of the assembly line design for the pipeline-level replication logic. The method of "folding Pipeline" is the opposite of "disassembling the loop", and is an area and speed interchange method.

2. shared logical resources sometimes require dedicated control circuits to determine which components are input to a specific structure. In some applications, resource input is often more complex. In order to reuse the logic, some controls may be necessary. When the sharing logic is larger than the control logic, control can be directly used for logic reuse.

3. Resource Sharing

Resource Sharing is not a low-level optimization performed by the FPGA layout and wiring tool, but a high-level structure Resource Sharing. Different resources are shared across different functional scopes.

For the area design, which is mainly required for the compact design, search for resources with similar counting components in other modules. You can place them in the Global Position of the hierarchy and share them directly across multiple functional ranges.

4. improper reset and placement policies can generate unnecessary large design and suppress some area optimization, based on the underlying structure of FPGA, we need to analyze whether we want to adopt Synchronous Reset/set bit, Asynchronous Reset/set bit, or not to reset/set bit.

Optimized FPGA resources will not be used when incompatible resetting is assigned to it, but more resources will be used to implement its functions using general components.

DSPs and other multi-functional resources are generally not flexible to change the reset policy. When Synchronous Reset is used, the integrated tool can use the available DSP cores in FPGA Devices. However, A large amount of logic needs to be generated to Implement Asynchronous Reset when it is different from the available reset in the device.

Resetting Ram is usually a poor design practice, especially when resetting or Asynchronization.

Ii. Power Consumption Structure Design

In CMOS technology, the dynamic power consumption is related to the charge and discharge of the parasitic capacitor of the metal lead. The general equation for the current consumption in the capacitor is

I = V x C x F

Where I is the total current, V is the voltage, C is the capacitor, F is the frequency

Therefore, these three key parameters must be reduced to reduce the drive current. In FPGA design, the voltage is usually fixed, and only the capacitance and frequency can be controlled. Capacitor C is directly related to the number of doors triggered at any time and the wiring length of these doors. frequency f is directly related to the clock frequency.

1. Clock Control

The most effective and widely used technology to reduce dynamic power consumption in synchronous digital circuits is to dynamically prohibit clock in a specific area, and this area in the data stream does not need to be activated at a specific level. We recommend that you use the trigger clock pin or the global clock selector MUX.

Clock Control resources such as trigger input or global clock multi-channel selector should be used instead of direct clock selection. Clock switching is a direct method to reduce dynamic power consumption, but it is difficult to implement and analyze time series.

Clock offset

Because the signal may spread along the same clock through level 2 and level 3 (Figure 3-2), this will cause a sudden failure of the circuit. Therefore, you must consider the clock offset when performing timing analysis. It is important to note that the clock offset is irrelevant to the clock speed. This issue of "Fly-through" will appear in the same way, regardless of the clock frequency.

The clock line must be removed from the global resource with a low offset and routed to the selected logic. Clock selection can cause a conflict of persistence and may or may not be corrected by the implementation tool.

The clock Buffer technology that provides the ability to properly balance the Clock Tree. This type of control always recommends clock interconnectivity with logical components.

2. To minimize the power consumption of the input device, the signal rise and fall time of the driver is minimized.

3. It is always an input buffer that is not used by an end. It never leaves an FPGA input buffer empty.

4. The dynamic power consumption decreases with the square of the core voltage, but the reduction of the voltage has a negative impact on the performance.

5 trigger triggered by double edge

Because the power consumption is proportional to the f triggered by the signal, it is expected to maximize the number of triggering functions of the high fan-out network cable. In most similar cases, a high fan-out network cable is a system clock, so any technology that lowers the clock frequency will have an astonishing impact on dynamic power consumption, the dual-edge trigger allows the designer to run the clock at half the original frequency.

However, double-edge triggers can only be used when they are provided as basic components.

6. There is no consumption of steady-state current on the serial end.