ARM Architecture and Assembly directives

"Teacher Zhu's IoT lecture" study notes

Study Address: www.zhulaoshi.org

(1).
ASIC-specific chips to programmable devices,
CPU at fixed frequency, read/parse/execute instructions,
Binary files are read by the CPU, and the internal CPU circuitry decodes the binaries,


(2).
The meaning of the instruction set to the CPU,
Assembly language: Machine instruction Mnemonic,
Machine instructions are designed by the CPU designer, the CPU internal circuit design is to realize the function of these instruction sets, the machine instruction is like the CPU API interface,
Different CPU machine instruction sets are designed differently,


(3).
The difference between RISC and CISC,
Cisc:complex instruction Set computer, provides a variety of instructions, generally from about 300,
risc:ruduced instruction Set computer, provides only the most basic instruction, ARM CPU commonly used instruction 30 or so,


(4).
The number of bits of the address bus for the CPU is determined by the CPU design,
CPU and memory connection is directly connected, high efficiency, fast,


Io peripherals connected to the CPU,
1.IO and Memory Unified addressing,
2. Stand-alone addressing, using dedicated CPU instructions to access a specific peripheral,


Von Neumann: PC, simple, safe and stable is the problem!
Harvard structure; ARM, complex (need unified planning link address, etc.), security and stability, the program is generally placed in ROM, flash, data is generally placed in RAM,


(5).
Registers belong to the hardware component of CPU peripheral, it is developed by hardware designer of CPU, it is the switch of programming control, it is an "API",
Universal register: is a component of the CPU,
Special function Register: SFR, which exists in the peripheral of the CPU,


Ways to access registers:
1. Compilation method,
Ldr r1,=0xe0200280
Str R0,[R1]
mov r0, #0
2.C language Way,
int *p = (int *) 0x30008000;
*p = 16;


(6).
Servers and other high-performance areas are currently dominated by Intel,
ARM architecture for Embedded,


(7).
The s5pv210 is an arm cortex-a8 architecture, 32-bit CPU, designed with 32 address lines and 32 data lines,
Address assignment, address mapping, see,

(8).
Norflash
Nandflash
Emmc/inand/movinand
Onenand
SD card/TF Card/MMC card
ESSD
SATA HDD


(9).
Memory
SRAM, power up directly,
DRAM, which requires initialization to be used,


External memory
Norflash: General use of boot media,
Nandflash: As with a hard disk, it needs to be initialized and read and written through the timing interface.


Pc:bios (Norflash) + hard disk (similar to nandflash) +dram,
Embedded: nand+dram+ built-in SRAM


s5pv210 nand+dram+ built-in sram+ built-in Irom,


Start-up process;
1.CPU reads and executes the code in Irom (BL0), does some basic initialization, and then judges and enters some kind of startup mode from which to read the boot code (BL1) to internal SRAM,
2. Run the up-step read boot code from the SRAM, then execute, BL1 this section of code initializes the NAND, then reads BL2 to Iram and then runs,
3. Run BL2 in Iram, initialize DRAM, then read OS from NAND to DRAM, then start OS,
See figure,

(10).
What did BL0 do?
1. Turn off the watchdog,
2. Initialize the command cache,
3. Initialize the stack,
4. Initialize the heap,
5. Initialize the block device copy function, there are several functions to support a variety of startup,
6. Set the SOC clock system,
7. Copy BL1 to internal Iram
8. Check the checksum of the BL1,
9. Jump to BL1 to execute,


Different levels of hibernation, figure 4,

Different start, Figure 5


(11).
Ompin choice, can not look,


(12).
7 Models of ARM,
User mode: Users
Privileged mode, Fiq,irq,supervisor (SVC, reset or soft interrupt), Abort (Access exception), Undef,system,
Exception mode: Privileged Mode-system,


Mode switching and registers are different, automatic switching or through CPSR,


Software design to rely on the characteristics of hardware, hardware design to consider software needs, operating system has security level requirements, so the CPU design a variety of models is to facilitate the operating system of various role security level requirements,


(13).
ARM's 37 registers,
Figure 6, register, shadow register (banked register), in different modes, have the same name as the register, actually not the same one,

Figure 7,CPSR,


(14).
One of the exceptions at break,
Exception vector table, CPU design time fixed, hardware decision, for software processing exception to provide support,
Figure 8,


(15) ~ (16).
Instructions
To instruct the compilation process, not to generate machine code after compiling,


ARM compilation style; LDR R0,[r1]
GNU compilation style: Ldr R0,[R1]


LDR/STR Architecture, RISC architecture The CPU itself does not directly read memory, but needs to load the in-memory content into the CPU General register before being processed by the CPU.
The LDR (load register) instruction loads the contents of the memory into a universal register,
The STR (store register) instruction stores the register contents in memory space,


8 ways of addressing;
Register addressing:MOV r1,r2
Immediate addressing: mov r0, #0xFF00
Register shift Addressing mov R0,r1,lsl#3
Register Indirect Addressing LDR R1,[R2]
Base Address variable address addressing Ldr R1,[r2, #4]
Multi-Register addressing Ldmia R1!,{r2--r7,r12} Loaded into R1, R1 can be understood as an array,
Stack addressing Stmfd Sp! , {R2-R7,LR}
Relative addressing: Beq Flag Flag is a label,


Instruction suffix:
B (Byte), function unchanged, operation length changed to 8 bits,
H (half word), function unchanged, operation length changed to 16 bits,
S (Signed), function unchanged, operand changed to signed number,
s (s sign, rest assured and not repeat above), function unchanged, affect CRSR flag bits, such as MOV and Movs,

Moveq R1,r2
Conditional execution suffix:
1. The conditional execution suffix is not determined by the code, but depends on the result of the code running before the code,
2. The conditional suffix determines whether the code of this sentence is executed, does not affect whether the previous sentence and the next sentence are executed,


Pipeline: 3-level (refer to, decode, execute) pipeline, PC and executing instruction difference (3-1=2) cycles,


(17).
MOV r1,r0 @ Pass data between two registers
mov r1, #0xff @ Assigns an immediate count to the Register


The MOV,MVN difference is the bitwise inversion,


Eor Logical XOR,


Bit Bit clear,
Bic R0,R1, #0x1f@ R1 The number of bit0 to BIT4 after 0 is assigned to R0,


Mrs (read), MSR (write), CPSR access instruction,
Mrs R0,cpsr
@...
@ R0 Median value is processed
@...
Msr Cpsr,r0


B Direct Jump,
Bl Jump and save the return address to LR,


Multi-word bulk access,
Ldm/stm


Number immediately, plus # in front,
Legal immediate number: After the shift is not 0 not more than 8 bits,


Swi,software Interrupt,


(18).
MCR (Write), MRC (read), read/write coprocessor,
Coprocessor and mmu,cache,tlb and other processing related, functional and operating system virtual address mapping, cache management and so on,


The usage was so strange,
/*
* Disable MMU stuff and caches
*/
Mrc P15, 0, R0, C1, C0, 0
Bic R0, R0, #0x00002000 @ clear bits (--v-)
Bic R0, R0, #0x00000007 @ clear bits 2:0 (-CAM)
Orr R0, R0, #0x00000002 @ set bit 1 (--a-) Align
Orr R0, R0, #0x00000800 @ set bit (Z---) BTB
McrP15, 0, R0, C1, C0, 0

(19).
LDR/STR can access only 4 bytes of memory per cycle,
So, there
LDM (Load Register mutiple),
STM (store register mutiple),
There are many suffixes, irritability ~ia ah, ib Ah,


Empty stack/Man,
Add/Subtract stacks,




LDMFD sp! , {r0-r6,pc}
LDMFD sp! , {r0-r6,pc}^
！ The value in the SP is stored in the change,
^ function, when there is a PC in the target register, the SPSR is written to CPSR, which is generally used to return from the exception mode.
We used to Stmia and STMFD,


(20).
@ Here is the note, the following is the label,
FLAG:B Flag
Or
B.
. Represents the current address,
#0x1f @ This is an immediate number
. globl _start @ Add external link properties,
. Word @ can be treated as unsigned int
. Align 4 @2^4=16 byte alignment,
. end @ Identity File End
. Include The @ header file contains


Ldr Large range Address loading instructions
Adr Small range Address loading instructions
Adrl Medium-range address loading directives
Nop NULL instruction

ARM Architecture and Assembly directives