ARM architecture and assembly 100 (1)

Chapter 4 Architecture

1st Q:
Q: What is the processor mode when executing the mov R0 and LR commands at the beginning of CPU stack initialization?
A: The reset mode, that is, the management mode.

2nd Q:
Q: How does 0xf0000001 obtain the number of 8 bitmap values in mov?
A: shifts the right of a loop, that is, the number between 0 and 255 shifted to the left or the number of even digits shifted to the right, that is, the number is divided by 4, it is okay if it is an integer in the range of 0!
A: the result of an 8-digit (0-255) loop shift left or an even number of digits shift right. f0000001 is correct because it is both 0x1f loop and 4 bits shift right. this is because of the limit on the instruction length, it is impossible to put the 32-bit immediate number in the 32-bit instruction.

This is also the reason for the shift of even numbers. You can take a look at the relevant section of the ARM architecture (the English documentation provided by ADS.

3rd Q:
Q: Please refer to Section 2.2.1 "ARM microcontroller basics and Practices" for the description of the 2nd operands:
# Inmed_8r constant expression. This constant must correspond to an 8-Bit Bitmap, that is, Changshu is obtained by an 8-bit constant cyclic shift of an even number.
Valid constants: 0x3fc, 0, 0xf0000000, 200, 0xf0000001.
Invalid constant: 0x1fe, expires, 0 xFFFF, 0x1010, 0xf0000010.
Example of constant expressions:
...
...
LDR r0, [R1], #-4; reads the content of the memory unit on the R1 address, and R1 = R1-4
In response to this paragraph, I have the following questions:
1. That is, the constant is obtained by an eight-bit constant cyclic shift to an even number.
2. The constant must correspond to an 8-Bit Bitmap. Since it is an 8-Bit Bitmap, the value ranges from 0 to 255. How can I create a valid constant for a number greater than 255 such as 0x3fc?
3. In the example above, how do we distinguish between valid constants and illegal constants? For example, 0x3fc is legal, while 0x1fe is invalid, 0xf0000000 and 0xf0000001 are both legal, and 0xf0000010 becomes invalid again.
4. for an assembly statement LDR r0, [R1], #-4, the result of first reducing the value of R1 by 4 is saved to R1, and then reading the value of the unit indicated by R1 to r0, read R1 to R0 first, and then save R1 minus 4 to R1.

A: It is prompted that any constant can be expressed by the N power of base number * 2.
1. In the arm structure, only 8 bits are used to represent the base number. Therefore, the base number must be an 8-Bit Bitmap.
2. The constant is obtained after an 8-Bit Bitmap loop. It is not only 8-bit.
3. 0xf0000010 the base number is 9 BITs, which cannot be expressed.
4. LDR r0, [R1], #-4 is the suffix index, that is, read first, and then subtract.
Let's take a look at the description of the relevant addressing methods in the ARM architecture.

4th Q:
Q:ProgramWhat is the migration process?CodeThe pattern of the segment is really a difficult problem. Is there a way to identify the pattern of the segment"
A: Read CPSR. It can be read at any time.

5th Q:
Q: Why always protect the R0-R3, R12 when protecting the site, why not protect the R4-R11?
A: Please take a look at the document "arm-thumb process call standard.

6th Q:
Q: May I ask mov R1, #0x00003dd0 error: out of the range of operation? I just want iodir = 0x00003dd0, assembly is
LDR r0, = iodir
MoV R1, #0x00003dd0
STR R1, [R0]
During compilation, the operation is out of scope.
A: LDR and mov are used to return 8 bitmap values.

7th Q:
Q: "There are 37 user-visible registers in the ARM7TDMI (-S) processor :"
Question: "user-visible" How should we understand whether these 37 registers are 37 different physical registers,
For example, R8 and r8_fiq should be two different physical registers.
A: You can see that the. R8 and r8_fiq registers that users can operate through programs are different.

8th Q:
Q: What are the limits of USR, SVC, and IRQ modes?
A: The peripheral operation restrictions are related to the chip design. CPSR registers cannot be set in USR mode. spsr registers are not available in user mode. The code can be arm or thumb.

9th Q:
Q: What does "the working mode is determined when the stack is initialized" mean? How is the working mode determined?
A: Set the CPSR register.

10th Q:
Q: What is the so-called "text pool" in arm assembly programming?
A: It can be understood as a constant array. constants are saved in the text pool. These constants can be normal constants or addresses.

11th Q:
Q: Why do ldr pc and "abnormal address" are not used in the interrupt vector table, but a label is used, and then DCD is used later to define this label?
A: Because the LDR command can only jump to the current PC 4 kb range, while the B command can jump to the 32 MB range, and now in the LDR PC, "XXXX" this command defines a word with "XXXX" DCD, which stores the final exception service program.

To achieve full range jump of 4 GB.
Q: Isn't LDR capable of Full-space jump? List of programs in "ARM microcontroller basics and Practices" 5.3.
A: LDR pseudo-commands can achieve full range jump only by setting the instruction buffer pool, while LDR commands can only achieve a 4 kb range jump.

12th Q:
Q: What is the difference between ARM7TDMI-S and ARM7TDMI?
A: The ARM7TDMI-S is the integrated (synthesizable) version of ARM7TDMI ). for application engineers, the ARM7TDMI-S and ARM7TDMI are not much different unless the chip manufacturers cut the ARM7TDMI-S.

The model is consistent with ARM7TDMI.

13th Q:
Q: What is the meaning of the program label or digital expression behind the DCD? "stackusr DCD usrstackspace + (usr_stack_le1_1) * 4"
A: Its content is the highest address for initializing the decreasing stack. For details, see section 2.3.2 of ARM microcontroller basics and practices.