Arm assemble register

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Arm Assembly programming is essentially a programming of CPU registers. So we need to first find out what registers arm has? How are these registers used?

Arm registers are classified into two types: common registers and status registers.

Register Type
Register name in assembly
Registers actually accessed in each mode
 
User
System
Management
Abort
Undefined
Interrupted
Fast interruption
 
General registers and program counters
R0 (A1)
R0
 
R1 (A2)
R1
 
R2 (A3)
R2
 
R3 (A4)
R3
 
R4 (V1)
R4
 
R5 (V2)
R5
 
R6 (V3)
R6
 
R7 (V4)
R7
 
R8 (V5)
R8
R8_fiq
 
R9 (SB, V6)
R9
R9_fiq
 
R10 (SL, V7)
R10
R10_fiq
 
R11 (FP, V8)
R11
R11_fiq
 
R12 (IP)
R12
R12_fiq
 
R13 (SP)
R13
R13_svc
R13_abt
R13_und
R13_irq
R13_fiq
 
R14 (LR)
R14
R14_svc
R14_abt
R14_und
R14_irq
R14_fiq
 
R15 (PC)
R15
 
Status Register
CPSR
CPSR
 
Spsr
None
Spsr_abt
Spsr_abt
Spsr_und
Spsr_irq
Spsr_fiq
 

 

Please refer to the above table's 2nd columns, a total of 16 General registers, respectively for the R0-R15; a total of 2 State registers, CPSR and spsr respectively

In general registers, R13, R14, and r15 are particularly proposed.

R15 alias PC (program counter), which is called a program counter in Chinese. Its value is the position of the currently executed command in the memory (regardless of the influence of the pipeline, see the article on the impact of pipelines on PC values). When the command execution ends, the CPU hardware will automatically add a unit to the PC value, so that the value of the PC is the location of the next command to be executed in the memory, so that the CPU hardware can automatically perform the finger fetch operation based on the value of the PC. It is precisely because of the existence of a PC, and the CPU hardware will automatically increase the value of the PC, and the retrieval operation is completed based on the value of the PC, so that once the CPU is powered on, it will never stop running, it can be seen that PC registers are important to computers. PC registers are also very important for us to compile assembler programs, because when programmers assign values to PC registers through assembly instructions, they actually complete an unconditional jump, this is very important, so be sure to keep it in mind.

The R14 alias LR (linked register) is called a link register in Chinese. It is closely related to subprogram calls and is used to store the return address of subprograms. It is the key to implementing subprogram calls in arm programs. The following describes how LR is used using the Implementation Details of subroutine calls in C language.

1 int main (void)
2 {
3 int K, I = 1, j = 2;
4 addsub (I, j );
5 K = 3;
6}

7 int addsub (int A, int B)
8 {
9 int C;
10 C = A + B;
11 return C;
12}

For the above program, the compiler will compile 4th lines as the command: BL addsub, and 11th lines as the command: mov PC, LR. (For BL and mov commands, see "Basic addressing mode and basic commands ")

Here, the key command BL addsub will accomplish two things: 1. Save the return address of the subroutine (that is, the location of the 5th-line code in the memory) to the Register LR; 2. Jump to the Second instruction in the subprogram addsub. In this way, the subroutine is called. In the mov PC command, LR assigns the return address stored in lr to the PC, which completes the return from the subroutine. It can be seen that LR is used to store the return address of the subroutine.

Another issue that should be noted is that if the subroutine calls the Sun Tzu program again, according to the previous analysis, when the Sun Tzu program is called, the value in the LR register changes from the return address of the subroutine to the return address of the grandson program. This will cause no problem in returning the subroutine from the grandson program, but returning the parent program from the subroutine will cause an error. How can this problem be solved? In fact, if we write a C program, we don't have to worry about it at all, because the compiler will consider everything for us, the compiler adds the stack operation at the entrance of the Sun Tzu program to stack the LR value, and then adds the stack operation at the back of the Sun Tzu program to restore the LR value, to solve this problem. However, we must be clear-headed, because you need to know that we are writing Assembly subprograms. At this time, the compiler cannot provide us with assurance in this respect, so when you write an assembly subroutine and find that the subroutine needs to call the grandson program again, remember that the LR register value must be saved at the entrance of the subroutine.

Now it's the turn of register R13, R13, also known as SP (Stack pointer), Chinese name pallet pointer register. As the name suggests, it is used to store the top stack address of the stack. That is to say, each time when we perform the out-of-stack and In-stack operations, we will determine the location of the access memory based on the value of this Register (that is, the location of the memory in and out of the stack ), at the same time, the SP register value should also be increased or decreased after the operation is completed. In fact, the 32-bit arm instruction set does not have any special inbound and outbound commands, so it is not necessary to use SP as the stack pointer register, in addition to PC, any common register can be used as a stack pointer register, but SP is used in general. In the article "other addressing modes and other commands", we will see the inbound and outbound commands using SP in arm as the stack pointer register.

Register R0-R12 is a common data register that can be used anywhere. They do not have any special usage when they do not involve the atpcs rules (detailed in "atpcs and mixed programming.

Status Register CPSR (current Program Status Register), Chinese name: current program status register, as the name suggests, it is used to save the current state of the program. So what States do programs need to be saved?

Is the content of the CPSR register, mainly composed of the following parts:

1. Condition code flag. They are the basis for executing arm command conditions.

N: The highest bit of the calculation result is reflected in this flag. For signed binary complement, if the result is negative, n = 1, and the result is positive or zero, n = 0;

Z: When the command result is 0, Z = 1 (usually the comparison result is "equal"); otherwise, Z = 0;

C: When the addition operation (including the CEN command) is performed and the highest bit produces carry, c = 1; otherwise, c = 0. When subtraction (including CMP commands) is performed and the maximum bits are generated, c = 0; otherwise, c = 1. For non-addition/subtraction commands that combine the shift operation, C is the value that is removed from the maximum bit. Other commands C are usually unchanged.

V: When an addition or subtraction operation is performed and a signed overflow occurs, V = 1; otherwise, V = 0. Other commands do not change.

2. Control bit. They will control whether the CPU responds to interruptions.

I: indicates the position where the IRQ is interrupted.

F: indicates the fast interruption prohibition bit. When the f position is specified, the FIQ interruption is disabled.

T: indicates the current CPU status. When the t position is reached, the processor is running in the thumb state; when the T position is cleared, the processor is running in the arm state.

3. Mode bit

Including M4, M3, M2, M1, and M0, which determine the processor mode (for details about the processor mode, refer to the article "ARM processor mode and exception preliminary ).

There are 7 modes in total: User, fast interrupt, interrupt, management, abort, undefined, and system, which are used for different situations and exceptions respectively. It can be seen that not all combinations of mode bits define a valid processor mode. If incorrect settings are used, an unrecoverable error will occur.

Spsr (saved Program Status Register), Chinese name: saved Program Status Register

The structure of this register is exactly the same as that of CPSR. When an exception occurs (for details about the exception, see "ARM processor mode and exception preliminary ), the hardware automatically stores the CPSR value before the exception occurrence in spsr, so that the program can restore the original CPSR value after the Exception Processing is completed in the future.