ARM assembly Instructions MCR/MRC Learning

The MCR instruction arm data register is transmitted to the coprocessor register. Assume that the coprocessor cannot run the operation successfully. An undefined instruction abort is generated.

Grammar teaching Format:

Mcr{<cond>} p15, 0, <rd>, <crn>, <crm>{,<opcode_2>}

MCR2 P15, 0, <rd>, <crn>, <crm>{,<opcode_2>}

Of <cond> the condition code to run for the instruction. Commands are run unconditionally when <cond> is ignored. MCR2 in,<cond> is Ob1111, instruction is unconditional run instruction.

<opcode_1> The operation code for the operation that the coprocessor will run.

For the CP15 coprocessor, <opcode_1> is always 0b000, and when <opcode_1> is not 0b000, the command operation results are unpredictable.

<Rd> Arm Register as a meta register. Its value is transferred to the coprocessor register.

<Rd> cannot be a PC. When it is a PC. The command operation result is unpredictable.

<CRn> is the coprocessor register of the target register, the number may be c0,c1 .... C15.

<CRm> additional target register or the original operand register. Different physical registers used to differentiate the same number.  When no additional information is required in the instruction, the C0 is specified as <CRM>, otherwise the instruction operation result is unpredictable. <opcode_2> provides additional information for different physical registers that differ from one number to another. Omit <opcode_2> or specify 0 when additional information is specified in the instruction, otherwise the instruction operation result is unpredictable.

The MRC instruction transfers the value of the coprocessor's registers to the registers of the ARM processor. Assuming that the coprocessor does not successfully run the operation, it will result in an abnormally broken instruction without a definition.

Syntax format for directives:

Mrc{<cond>} p15, 0, <rd>, <crn>, <crm>{,<opcode_2>}

MRC2 P15, 0, <rd>, <crn>, <crm>{,<opcode_2>}

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ARM assembly Instructions MCR/MRC Learning