Arm bus interface and Memory Hierarchy

The three-level flow organization in arm: Take the pointer --> decoding --> execute the five-level flow organization in arm: --> decoding --> execution --> buffer \ data --> interface for writing back arm memory and its hierarchy: the data types supported by the basic arm that MMU implements virtual memory management:
8, 16, 32-Bit Signed numbers and unsigned numbers are aligned in two or four bytes. 8-bit: signed charunsigned char

16-bit: shortunsigned short
32-bit: intunsigned int
Arm memory layers:
Register group on-chip RAM on-chip cache master memory Hard Disk
Arm coprocessor: Implements function expansion of the arm in-chip bus:
1) AHB (advanced high-performance bus) is used to connect high-performance modules. It supports abrupt data transmission mode and single data transmission mode. All Time Series refer to the same clock edge. Burst data access refers to one addressing and transmission of multiple data. Single-byte access refers to one addressing and one data transmission. 2) asb (Advanced System Bus): High-Performance module, SDRAM, In-chip ram.3) APB (Advanced Peripheral Bus): Low-performance device, external dram, etc.
"CPU core" includes ARM core, Cache Management, MMU management, and so on...
Currently, the following six arm series products are available:
Arm7arm9arm9earm10esecurcorearm11
Launched by Intel:
Strongarmxscale

ARM7TDMI
ARM7: 32-bit ARM architecture 4 t version T: "thumb" D: debugm On-Chip: enhanced multiplieri: On-Chip breakpoint and observation point