Arm coprocessor CP15 (set MMU, cache, etc.) Learning

Author: wogoyixikexie @ gliet

I am always afraid of the coprocessor CP15 because I cannot find detailed instructions on Chinese on the Internet. Now I have found some official arm documentation (ARM920T Technical Reference Manual, prepare to end it.

The coprocessor CP15 contains the following registers.

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The following key terms are available in ARM920T Technical Reference Manual:

2.3.1 addresses in ARM920T
Three distinct types of address exist in an ARM920T system:
• Virtual address (VA)
• Modified virtual address (MVA)
• Physical address (PA ).
Below is an example of the address manipulation when the arm9tdmi core requests
An instruction (see Figure 2-10 on page 2-25 ).
1. The instruction VA (IVA) is issued by the arm9tdmi core.
2. This is translated by the procid to the instruction MVA (imva). It is the imva
That the instruction cache (icache) and MMU see.
3. If the protection check carried out by the immu on the imva does not abort, and
The imva tag is in the icache, the instruction data is returned to the arm9tdmi
Core.
4. If the icache misses (the imva tag is not in the icache), then the immu
Performs a translation to produce the instruction PA (IPA). This address is given
To the AMBA bus interface to perform an external access.

_________________________________________________ I will not translate these things in detail, so as not to miss people.

2.3.2 accessing CP15 registers access CP15 registers
The terms and abbreviations (acronyms) shown in Table 2-4 are used throughout this section.
Table 2-4 CP15 abbreviations
Term abbreviation description
Unpredictable UNP

For reads, the data returned when reading from this location is unpredictable. It can
Have any value.
For writes, writing to this location causes unpredictable behavior, or an unpredictable
Change in device configuration.
Shocould be zeroSbz

When writing to this location, all bits of this field shocould be 0.

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You can only access CP15 registers with MRC and MCR instructions in a privileged mode. (privileged Mode)

MCR/MRC {cond} P15, opcode_1, RD, CRN, CRM, opcode_2

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Instructions CDP, LDC, and STC, together with unprivileged MRC and MCR instructions to CP15, cause the undefined instruction trap to be taken (leading to undefined ...). the CRN field of MRC and MCR instructions specifies the coprocessor register to access. the CRM field and opcode_2 fields specify a special action when addressing registers. the l bit distinguishes between an MRC (L = 1) and an MCR (L = 0 ). -- indicates the CRN And CRM.

 

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Note
Attempting to read from a nonreadable register, or to write to a nonwritable register causes unpredictable results.
TheOpcode_1, opcode_2, and CRMFields shoshould be zero, should t when the values specified are used to select the desired operations, in all instructions that access cp15. using other values results in unpredictable behavior.

-- What is the purpose here? Wait until you see the code below.

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Register 0, ID code register (read chip 32-bit ID)
This is a read-only register that returns a 32-bit device ID code.
You can access the ID code register by reading CP15 register 0 with the opcode_2 field set to any value other than 1 (the CRM field shocould be zero when reading). For example:

MRC P15, 0, RD, C0, C0, 0; returns ID register

-- Chip ID meaning

Table 2-5 register 0, ID code
Register bits function value
31: 24 -- implementer 0x41 -- what does this mean?
23: 20 -- specification Revision 0x1
19: 16 -- Architecture (armv4t) 0x2
15: 4 -- part number 0x920
3: 0 -- layout revision Revision

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2.3.4 register 0, cache type register

This is a read-only register that contains information about the size and architecture
The caches, allowing operating systems to establish how to perform such operations
Cache cleaning and lockdown. All armv4t and later cached processors contain this
Register, allowing RTOS vendors to produce future-proof versions of their operating
Systems.

You can access the cache type register by reading CP15 register 0 with the opcode_2 Field
Set to 1. For example:
MRC P15, 0, RD, C0, C0, 1; returns cache details

-- It seems that this topic is very complicated, and it is useless for me to write it. The most important thing is that I am very likely to make an error, so I will stop this blog.

If you have any questions, please post on the forum or refer

ARM920T Technical Reference Manual -- http://download.csdn.net/source/903240

Reprinted please indicate: The author wogoyixikexie @ gliet. Guilin University of Electronic Science and Technology Department 1 Association of Science and Technology, original address: Workshop.