Arm cortex-M instructions

Source: Internet
Author: User
Tags mul
Arm cortex-M Instruction Sets
Arm
Cortex-m
Thumb Thumb-2 Hardware
Multiply
Hardware
Divide
Saturated
Math
DSP
Extensions
Floating-point Arm
Architecture
Core
Architecture
Cortex-M0
Most Subset 1 or 32 cycle No No No No ARMv6-M
Von norann
Cortex-M0 +
Most Subset 1 or 32 cycle No No No No ARMv6-M
Von norann
Cortex-M1
Most Subset 3 or 33 cycle No No No No ARMv6-M
Von norann
Cortex-M3
Entire Entire 1 cycle Yes Yes No No ARMv7-M
Harvard
Cortex-M4
Entire Entire 1 cycle Yes Yes Yes Optional ARMv7E-M
Harvard
Cortex-M4F Entire Entire 1 cycle Yes Yes Yes Yes ARMv7E-M Harvard

Note: The Cortex-M0/M0 +/M1 doesn't include theseThumbInstructions:
CBZ, cbnz, it; nor does it include a divide instruction.

Note: The Cortex-M0/M0 +/M1 only include theseThumb-2Instructions:
DMB, DSB, ISB, Mrs, MSR.

Note: If a smaller silicon die size is required, the Cortex-M0/M0 +/M1
Can implement a smaller and slower multiply instruction.

All four cortex-m cores implement a common instruction subset that consists:

Thumb subset, thumb-2 subset, and multiply.

The Cortex-M0/M0 +/M1 include all older thumb instructions,
Using t new instructions (CBZ, cbnz, It) which were added in ARMv7-M architecture.

The Cortex-M0/M0 +/M1 include a minor subset of thumb-2 instructions
(BL, DMB, DSB, ISB, Mrs, MSR ).

The Cortex-M0/M0 +/M1 were designed to be the smallest size possible,
Thus having the fewest instructions of the cortex-M family.

The Cortex-M3 adds 3 thumb instructions and all thumb-2 instructions,
Plus a 10-12 cycle hardware divide and saturated math instructions.

The Cortex-M4 adds DSP instructions and an optional single-precisionfloating-point unit.

If the Cortex-M4 has the floating point unit, then it is known as the Cortex-M4F.

Arm cortex-M instructions
Instructions Instruction
Size
Cortex
M0
Cortex
M0 +
Cortex
M1
Cortex
M3
Cortex
M4
Cortex
M4f
ADC, add, ADR, And, ASR, B, Bic, bkpt, blx, BX, CEN, CMP, CPS, EOR, LDM, LDR, ldrb, ldrh, ldrsb, ldrsh, LSL, LSR, mov, Mul, MVN, NOP, Orr, Pop, push, Rev, rev16, revsh, Ror, RSB, SBC, SEV, STM, stmia, STR, strb, strh, sub, SVC, sxtb, sxth, TST, uxtb, uxth, WFE, WFI, yield 16-bit Yes Yes Yes Yes Yes Yes
BL, DMB, DSB, ISB, Mrs, MSR 32-bit Yes Yes Yes Yes Yes Yes
Cbnz, CBZ, it 16-bit No No No Yes Yes Yes
ADC, add, ADR, And, ASR, B, BFC, BFI, Bic, CDP, clrex, clz, CEN, CMP, dbg, EOR, LDC, ldma, ldmdb, LDR, ldrb, ldrbt, ldrd, ldrex, ldrexb, ldrexh, ldrh, ldrht, ldrsb, ldrsbt, cosine, ldrsh, ldrt, MCR, LSL, LSR, MLS, mcrr, MLA, mov, movt, MRC, mrrc, Mul, MVN, NOP, ORN, Orr, PLD, pldw, PLI, Pop, push, rbit, Rev, rev16, revsh, Ror, rrx, RSB, SBC, sbfx, sdiv, SEV, smlal, smull, SSAT, STC, analytic dB, STR, strb, strbt, strd, strex, strexb, strexh, strh, strht, strt, sub, sxtb, sxth, TBB, tbh, TEQ, TST, ubfx, udiv, umlal, umull, usat, uxtb, uxth, WFE, WFI, yield 32-bit No No No Yes Yes Yes
Vabs, vadd, vcmp, vcmpe, vcvt, vcvtr, vdiv, vldm, vldr, vmla, vmls, vmov, vmrs, vmsr, vmul, vneg, vnmla, vnmls, ingress, vpop, vpush, vsqrt, vstm, vstr, vsub 32-bit No No No No No Yes

Arm cortex-M instructions

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