Arm exam exercises

I. multiple choice questions

1. Arm belongs to ()

[A] RISC architecture [B] CISC architecture

2. The arm instruction set is (c) Bit width, and the thumb instruction set is (B) Bit Width.
[A] 8-bit [B] 16-bit [c] 32-bit [d] 64-bit

3. The arm instruction set is (h) byte alignment, and the thumb instruction set is (f) byte alignment.
[E] 1 [f] 2 [g] 3 [H] 4

4. After resetting, the ARM processor is in the (B) mode and (d) state.
[A] user [B] SVC [c] system [d] Arm [e] thumb

5. the ARM processor has a total of (e) registers. (a) registers are used in system mode, and (B) registers are used in SVC mode.
[A] 17 [B] 18 [c] 32 [d] 36 [e] 37

6. The highest priority exception in the ARM processor is (E), and the (AC) exception can be used for corresponding interruptions.
[A] FIQ [B] SWI [c] IRQ [d] SVC [e] Reset

7. The valid immediate number in arm data processing commands is (acegh)
[A] 0x00ab0000 [B] 0x0000ffff [c] 0xf000000f [d] 0x08000012
[E] 0x00001f80 [f] 0 xffffffff [g] 0 [H] 0xff000000

8. In atpcs, the maximum number of subfunction parameters recommended is (d ).
[A] 1 [B] 2 [c] 3 [d] 4

9. In atpcs, stack is (B)
[A] full addition [B] Full subtraction [c] Blank addition [d] Blank Subtraction

10. In arm assembly programming, its registers have multiple aliases. Generally, PC refers to (d), LR refers to (c), and SP refers to (B)
[A] R12 [B] R13 [c] R14 [d] R15

11. The bit in the CPSR register that reflects the processor status is (d)
[A] J-bit [B] I-bit [c] F-bit [d] T-bit

12. Which of the following commands are called by the arm subroutine? (c)
[A] B [B] BX [c] BL [d] mov

13. ARM7 belongs to the (a) structure, while ARM9.
[A] von noriman [B] Harvard

14. ARM7 Is A (B)-level assembly line, while arm9-is A (c)-level assembly line.
[A] 1 [B] 3 [c] 5 [d] 7

15. In arm, the command that can access the Status Register is (d), and the command that can access the memory is (B)
[A] mov [B] LDR [c] MCR [d] Mrs

16. The data bit in the asynchronous serial port can be (ABCD)
[A] 5 [B] 6 [c] 7 [d] 8

17. I2C protocol has several threads (B)
[A] 1 [B] 2 [c] 3 [d] 4

18. In I2C protocol, the device address mode is (AC)
[A] 7-bit address mode [B] 8-bit address mode [c] 10-bit address mode [d] 4-bit address mode

19. The S3C2410 adopts the (d) core.
[A] ARM7TDMI [B] arm9tdmi [c] ARM926EJ-S [d] ARM920T

20. In Serial Asynchronous Communication, the txd of the sender serial port must be connected to (B) of the receiver serial port.
[A] txd [B] rxd [c] NCTS [d] nrts

21. In the embedded system design, the battery voltage can be measured by (B), and the speaker can be driven by (c ).
[A] DAC [B] ADC [c] PWM [d] timer [e] rtc

22. MMU functions (AB)
[A] memory protection [B] address translation [c] acceleration of access speed [d] security and confidentiality [e] Memory Allocation

23. The following DMA features are: (BC)
[A] CPU usage [B] bus occupation [c] No CPU usage [d] No bus occupation

24. Among the following devices are flash memory devices (AD)
[A] k9f1208u0m [B] max3232 [c] hy57v561620 [d] am29lv160d

25. I2C transmission is in (B) mode.
[A] ticket [B] Half Duplex [c] Full Duplex

Ii. Short answer

1. Briefly describe what the ARM core will do automatically when an arm exception occurs? What do we do when an exception is returned?
When an exception occurs, ARM core:
Copy CPSR to spsr _ <mode>
Set the appropriate CPSR bit:
Change processor status to arm status
Change the processor mode to the corresponding exception Mode
Set the interrupt prohibition bit to disable the corresponding interrupt (if needed)
Save the return address to LR _ <mode>
Set PC as the corresponding exception Vector

To return an exception, you must:
Recover CPSR from spsr _ <mode>
Recover a PC from LR _ <mode>
Note: These operations can only be performed in arm mode.

2. Use the arm assembly command to write the code segment that implements the 64-bit addition and 64-bit subtraction. Please allocate the registers you use.
Assume that the 32-bit low is stored in R0 and R1, and the 32-bit high is stored in R2 and R3.
Addition:
Adds r0, R0, R1 // Add s for this operation to affect the flag
ADC R2, R2, R3 // ADC is the addition of the incoming bit. If the previous command generates a carry value, it is added together.
Subtraction:
Subs r0, R0, R1 // Add s for this operation to affect the flag
SBC R2, R2, R3 // SBC is the subtraction command of the incoming bits.

3. List the mode and exception of the ARM processor, and describe the mode in which the ARM processor is located in case of any exception.
Exception:
Reset
Data abort
FIQ
IRQ
Prefetch abort
SWI
Undefined instruction
Processor Mode
User: Non-Permission mode. Most tasks are executed in this mode}
FIQ: when a high-priority (FAST)} interrupt occurs, it will enter this mode.
IRQ: This mode is enabled when a low-priority (normal) interrupt is generated}
Supervisor}: This mode is enabled when the reset or Soft Interrupt command is executed.
Abort: enters this mode when an access exception occurs}
UNDEF:} This mode is enabled when undefined commands are executed.
System: Use the privileged mode of the same register set as the user mode}

4. What features does FIQ process faster than IRQ?
1) FIQ has a higher priority than IRQ and will not be interrupted
2) FIQ has its own exclusive register: R8 ~ R12, without protection for the General Register into the stack, can speed up
3) FIQ is at 0x1c at the end of the exception vector table, so no jump is required. You can directly place the exception processing function here.

5. What commands can be placed on the interrupt vector table?
Jump command, the command assigned to the PC
B, LDR, mov

6. Where is the ARM processor's interrupt vector table located in the memory?
Default Value: 0x0.
You can also set it to 0xffff0000.

7. What will the following arm commands do?
A) ldrh r0, [R1, #6]
B) LDR r0, = 0x999
A: Add 6 to the value of the R1 register, and then assign the half-character (16-bit low) of the value in the memory unit with this value as the address to R0.
B: Assign the immediate number 0x999 to R0. Note that this is a pseudo command.

8. What are the advantages of the SWP command? What functions are used to implement?
Function: An atomic operation between a register and a memory, consisting of one memory read and one memory write. Completes the exchange of one byte or word.
It can be used to implement semaphores.

9. How many boot modes (or memory ing modes) are supported by S3C2410 )? This article briefly describes how the hardware of the NAND Boot Mode S3C2410 works.
1) nor flash startup mode.
2) NAND Flash startup mode.
When starting from NAND Flash, S3C2410 will first execute a small program solidified in the On-Chip Rom. This program is responsible for moving the first 2 k code of NAND flash to the on-chip RAM, then point the PC pointer to the 0x0 address (note that the on-chip RAM is mapped to the starting address of 0x0)

10. Briefly describe the meanings and functions of the static and volatile keywords.
The static keyword in C language has two functions: File Scope and function scope.
The keyword "static" in the file scope is used to indicate that the global variables and functions declared as static cannot be referenced by other files.
Static another purpose is to use static variables in a function only once, and the variables are stored in the global data segment rather than in the function stack. Therefore, the life cycle of static variables continues until the program exits.
A variable defined as volatile means that this variable may be unexpectedly changed, so that the compiler will not assume the value of this variable. Precisely, the optimizer must carefully re-read the value of this variable every time when using this variable, instead of using the backup stored in the register.