Arm exception, interruption, and analysis of their vector table

Author: wogoyixikexie @ gliet

In the past, I had been wondering how this "arm exception, disruption, and their vector table" was, and how they actually implemented it, I did not expect to see the arm system developer's Guide: Design and optimizing system software chapter about arm exceptions, interruptions, and their vector table. -- ARM Embedded System Development: the original English version of software design and optimization -- I personally think this is one of the best arm book translation in China, which is times better than du XX's arm architecture and programming. Although this book talks about software design and optimization, it also talks about a lot of hardware, such as MMU and cache. It is brilliant: I just wanted to write a blog about MMU and cache, and I found it too huge, it seems that this book can only be written after reading it again.
:Http://download.csdn.net/source/904273
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-------- Let's take a look.

2.4 exceptions, interrupts, and the vector table

When an exception or interrupt occurs, the processor sets the PC to a speci memory C memory
Address. The address is within a special address range called the vector table. The entries
In the vector table are instructions that branch to speci operate C routines designed to handle
Particle exception or interrupt.

-- When an exception or interruption occurs, the processor sets the PC as a special memory address. This address is called the interrupt vector table. The entry to the interrupt vector table is the entry to the interrupt and abnormal branches (* ^__ ^ ......, This translation is poor, but everyone knows it ).

The memory map address 0x00000000 is reserved for the vector table, a set of 32-bit
Words. On some processors The vector table can be optionally located at a higher address
In memory (starting at the offset 0xffff0000). Operating systems such as Linux and
Microsoft's embedded products can take advantage of this feature.

-- Memory ing address 0x00000000 is reserved for the interrupt vector table. In some processors, the interrupt vector table address is 0xffff0000. Some operating systems such as Linux can use this feature (in fact, WinCE uses 0xffff0000 as the address of the interrupt vector table, however, it is strange that the address of the interrupt vector table of the ADS bootloader of youlong is 0x00000000, which is determined by the compiler ).

When an exception or interrupt occurs, the processor suspends normal execution and
Starts loading instructions fromthe exception vector table (see Table 2.6). Each vector table
Entry contains a form of branch instruction pointing to the start of a speci using C routine:

-- When an exception or interruption occurs, the processor suspends the normally executed program and starts to load the interrupt vector table. Each interrupt entry contains a routine pointing to speci Objective C (this does not know how to translate).

■ Reset vector is the location of the specified rst instruction executed by the processor when power
Is applied. This instruction branches to the initialization code.

-- Reset vector is the First Command executed by the processor when the power is turned on. This command is branches to initialize the code.
■ Unde specified Ned instruction vector is used when the processor cannot decode an instruction.

-- An undefined instruction vector is used when the processor cannot decode the instruction.
■ Software interrupt vector is called when you execute a SWI instruction. The SWI
Instruction is frequently used as themechanismto invoke an operating systemroutine.

-- Software interrupt vector ...... software interrupt commands are often used in operating system entries.
■ Prefetch abort vector occurs when the processor attempts to fetch an instruction Froman
Address without the correct access permissions. The actual abort occurs in the decode
Stage.

-- Prefetch termination vector when the processor attempts to obtain a command address without correct access permission, the actual termination occurs in the decoding phase
■ Data abort vector is similar to a prefetch abort but is raised when an instruction attempts
To access data memory without the correct access permissions.

-- The data termination vector is similar to the prefetch termination, but it occurs when the command attempts to access data and the memory does not have the correct access permission.
■ Interrupt request vector is used by external hardware to interrupt the normal execution
When ow of the processor. It can only be raised if irqs are not masked in the CPSR.

-- The interrupt request vector is used in programs where external hardware interruptions are normally executed. It can only be used when irqs are not blocked by CPSR.

 

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Summary: The interrupt vector search is implemented by hardware. The PC specified by the hardware jumps to 0xffff0000/0x00000000 (depending on the compiler). I used to learn from the software, which is a big mistake.

Reprinted please indicate: The author wogoyixikexie @ gliet. Guilin University of Electronic Science and Technology Department 1 Association of Science and Technology, original address: Workshop.