ARM Instruction Classification Learning

Instruction Category:

1. Arithmetic and logic instructions

2. Comparison instruction

3. Jump Instruction

4. Shift Instruction

5. Program Status Word access instruction

6. Memory Access Instruction

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Information on the instruction of the ARM compilation Manual (Chinese version). CHM, Note: This information is arm assembler manual, we use the GNU assembly, so the syntax is different in case.

Use the assembler in the previous article to learn the usage of each instruction.

First, arithmetic and logic instructions

1. mov instruction

function, format, example

Loads a value from another register, a shifted register, or an immediate value to the destination register.

mov{condition}{s}  <dest> <op 1>   . Where <dest> must be a universal register. The <op 1> can be a general-purpose register, or it can be an immediate number.

The assembler uses @ To add comments.

Jlink Connect the board, PC machine. Board Nandflash start. Turn on Jlinkgdbserver and start eclipse.
Open the Assembly program project in the previous article.

Edit the Start.s file directly in the Eclipse project,
. text
. Global _start
_start:
@mov Command Release
mov r1, #3
@ #3表示立即数, decimal 3
MOV r2,r1
MOV R3, #10

Clean, compile, Debug.
To view the value of the register, the value of the register can be displayed using the 16 binary, and the right-click menu option is set.

2, MVN: Transfer the value of the inverse

  mvn{Condition}{s}  <dest>, <op 1> (using the C language notation: dest =!op_1)  after the <op 1> bitwise reversed, Assigning value to <dest>

Example:
MVN R1, #ob10
@ #ob10 indicates binary number  10
MVN R2, #5
MVN R3,R1
------------------
The value of the R1 should be the value after the bitwise inversion of the binary 10:11111111111111111111111111111101

The value of the R3 should be the value of the R1 inverse of the binary  10

3, SUB: Subtraction

  sub{condition}{s}  <dest>, <op 1>, <op 2>                dest = op_1-op_2

SUBWith operand one minus the operand, The result is placed in the destination register. Operand 1 is a register, the operand 2 can be a register, a register that is shifted, or an immediate value

4, add: addition

5. And: Logic and

  and{condition}{s}  <dest>, <op 1>, <op 2>                dest = op_1 and op_2
----------------------------------

  Op_1   op_2   results  0      0      0  0      1      0  1      0      0  1      1      1
. text
. Global _start
_start:
mov r0, #0
mov r1, #1
mov R2, #3
and R3,R0,R1
The value of @r3 is 0
and R4,R1,R2
The value of @r4 is 1

6. BIC: Bit Clear

bic{conditions}{s}  <dest>, <op 1>, <op 2>
BICis a way to clear a bit in a word. The operand 2 is a 32-bit bitmask (mask). If one is set in the mask, this bit is cleared. A masked bit that is not set indicates that this bit remains unchanged.

Example:
The value of R0 is a binary  10111111
The Mask is   101.
The result is    10111010.
Mask is 1 clear corresponding bit, set to 0
If the mask is 0, the operation is not done.
. text
. Global _start
_start:
mov r1, #0b101011
Bic R2,r1, #0b101
The value of the @r2 should be 0b101010

Ii. Comparative directives

1. CMP: comparison (Compare)

The results of the comparison are saved in the program State Register, CPSR N, Z-bit

n:0 operand one is greater than the operand of

1 operand one is less than the operand of the number of

Z:1 indicates that the result of the comparison is two numbers equal

. text
. Global _start
_start:
mov r1, #1
CMP R1, #3

2. TST: Test bit
Operand one and operand two bitwise AND operation, results affect z-bit of CPSR

Status = Op_1 and op_2

Status 0  CPSR z-bit is 1

Status 1  CPSR z-bit is 0

Iv. Jump Instruction (branch instruction)

How is the If Else branch in the C language implemented in the assembler?

1, b

b{conditions} < address >
The knowledge of the {condition} is:

GT: Greater than (signed) if after a comparison ...
the N flag is set and the V flag is set
or ...
the N flag is cleared and the V flag is cleared
 and ...
The Z flag is cleared.
Example:
mov r1, #7
mov R2, #3
CMP R1,R2
BGT Branch
Add R3,R1,R2
b End
Branch
Sub R3,r1,r2
End
Nop

BGT branch: Satisfies the condition jumps to the branch marking place.

B End: Unconditionally jumps to the end label.

2. BL with connected branches

BL will save the address of the next instruction in the LR register. So that the function can return to the calling place normally.

Implement a function call in the assembly, return

MOV R3, #1

BL func1 @ CALL Function func1

mov r1, #6

FUNC1:

mov r1, #2

mov R2, #3

MOV PC,LR

@ Note the LR register, the BL instruction is able to save the next instruction of the jump address into the LR, can be disassembled to see the address of the LR is which instruction operation address.

MOV R3, #3

V. Shift directives

1.LSL logical left Shift

mov r1, #0b1

mov r1, R1, lsl#1

The value of the @r1 is eventually 0B10

2. ROR Loop Right Shift

mov r1, #0b11

mov r1, R1, ror#1

The final result of the @r1 1........1

VI. program Status Word access instruction

Special instructions are required to access and modify the CPSR register

MSR writes general-purpose registers to the CSPR register

Mrs Moves the program status Word to the general register

Mrs R0, CPSR @ assigns the value of CPSR to R0

Orr R0, #0b100 @ Place the third position of the r0 at 1

MSR CPSR, R0 @ assigns the value of R0 to CPSR

Vii. Memory Access Instructions

Memory value to register LDR

The value of the register to memory str

mov r0, 0xFF

STR r0, [R1] @ assigns the value of R0 to the memory of the address in the R1 value.

@ at debug time, the value of the modified R1 is considered to be 0x30001000, (2440 of the Development Board)

@ Debug Interface Open Memory window to see if the data address of 0x30001000 is 0xFF

LDR R2, [R1]

@ with the value of R1 as the memory address, the memory address on the value assigned to R2, should be 0xFF

ARM Instruction Classification Learning