ARM instruction Set 2

ARM instruction Set 2

The ARM microprocessor supports load/store instructions for transferring data between registers and memory, which is used to transfer data from memory to registers and the storage instruction to do the opposite.

LDR instruction (different from MOV, MOV can only operate universal Register)

The LDR instruction format is:

ldr{conditions} Destination register,< memory address >

The LDR directive is used to transfer a 32-bit word data from memory to the destination register. This instruction is typically used to read 32-bit Word data from memory to a general-purpose register and then process the data.

LDR R0, [R1]

Reads the word data with the memory address R1 into the register R0.

LDR R0, [R1,R2]

Reads the word data with the memory address R1+R2 into the register R0.

LDR R0, [R1, #8]

Reads the word data with the memory address r1+8 into the register R0.

LDR R0, [r1,r2]!

Reads the word data with the memory address R1+R2 into the register R0. and writes the new address R1+R2 to R1.

LDR R0, [R1, #8]!

Reads the character data with the memory address r1+8 into the register R0 and writes the new address r1+8 to R1.

LDR R0, [r1],r2

Reads the word data with the memory address R1 into the register R0. and writes the new address R1+R2 to R1.

LDR R0, [r1,r2,lsl#2]!

Reads the word data with the memory address r1+r2*4 into the register R0. and writes the new address r1+r2*4 to R1.

LDR R0, [r1],r2,lsl#2

Reads the word data with the memory address R1 into the register R0. and writes the new address r1+r2*4 to R1.

LDRB directive

The LDRB instruction format is:

ldr{Conditions}b Purpose Register,< storage Register >

The LDRB instruction is used to transfer a low 8-bit byte data from the register to the destination register, while the high 24 bits of the register are zeroed. This instruction is typically used to read 8-bit bytes from memory to a general-purpose register and then process the data.

instruction Example:

LDRB R0,[R1]; reads the number of bytes in the memory address of R1 into the register R0 and zeros the high 24 bits of the R0.

LDRB r0,[r1, #8]; reads byte data with a memory address of r1+8 into the register R0 and zeros the high 24 bits of R0.

LDRH directive

The LDRH instruction format is:

ldr{Conditions}h Purpose Register,< storage Register >

The LDRH instruction is used to transfer a low 16 bits of half-byte data from the register to the destination register, while the high 16 bits of the register are zeroed. This instruction is typically used to read a 16-bit half-byte count from memory to a universal register and then process the data.

instruction Example:

LDRB R0,[R1]; reads a half-byte memory address of R1 into the register R0, and zeros the high 16 bits of the R0.

LDRB R0,[R1,R2]; reads a half-byte data with a memory address of R1+R2 into the register R0, and zeros the high 16 bits of the R0.

STR command

The format of the str instruction is:

str{condition} Source register,< memory address >

The str instruction is used to transfer a 32-bit word data from the source register to memory.

instruction Example:

STR R0,[R1], #8; writes the word data in R0 to the R1-address memory and writes the new address r1+8 to R1.

STR r0,[r1, #8]; writes the word data in R0 to R1+8-address memory.

Bulk Load/Store instructions

The bulk data load/storage instructions supported by the ARM microprocessor can transfer data between successive storage units and multiple registers at once, and the bulk load instruction is used to transfer data from one contiguous memory to multiple registers, while the bulk data store instruction completes the opposite operation. The common load storage directives are as follows:

LDM Bulk Data Load Instructions

STM Bulk Data store directives

LDM Instruction

The LDM instruction format is:

The ldm{condition} {type} directive is used from the base address register {! }, register list {}

The LDM (or STM) instruction is used to transfer data from the contiguous memory indicated by the base address register to the plurality of registers indicated by the memory, and the common use of this instruction is to stack or stack the contents of multiple registers. where {type} is in the following cases:

｛！ } is an optional suffix, if the suffix is selected, the last address is written to the base register after the data has been transmitted, otherwise the contents of the base register will not change. The base register is not allowed for R15, and the register list can be any combination of r0~r15.

The register list {} is an optional suffix, and when the instruction is LDM and the Register list contains R15, the suffix is selected to indicate that the SPSR is copied to CPSR in addition to normal data transfer.

instruction Example:

STMFD r13! , {R0,R4-R12,LR}

The registers (R0,r4 to R12,LR) in the Register list are stored on the stack.

LDMFD r13! , {r0,r4-r12,pc}

Restores the stack contents to registers (R0,r4 to R12,LR).

Data exchange directives

The data exchange instructions supported by the ARM microprocessor can exchange data between memory and registers. The data Exchange directive has the following two articles:

SWP Word Data exchange directive

SWPB Byte data exchange instruction

SWP directive

The SWP instruction format is:

swp{conditions} destination registers, source registers 1,[source Register 2] or LDR and STR Two instructions can also implement SWP instructions.

The SWP instruction is used to transfer the word data in the memory pointed to by source Register 2 into the destination register, while transferring the Word data from source Register 1 to the memory pointed to in Source Register 2. Obviously, when the Meta Register 1 and the destination register are the same register, the instruction exchanges the contents of the register and memory.

instruction Example:

SWP R0,R1,[R2]; transfers the word data in the memory pointed to by R2 to R0, while transmitting the word data in R1 to the storage unit pointed to by R2.

SWP R0, R0, [R1]; This instruction completes the exchange of the word data in the memory pointed to by R1 with the word data in R0.

Shift Instructions

The ARM microprocessor supports the shift operation of data, and the shift operation is not used as a separate instruction in the arm instruction set, it is only a field in the instruction format and is represented as an option in the instruction in assembly language. The shift operation includes the following types, ASL and LSL are equivalent and can be freely interchanged:

LSL Logical left Shift

ASL Arithmetic left shift

LSR Logic Right Shift

ASR Arithmetic Right Shift

ROR Loop Right Shift

Exception generation Instructions

The exception commands supported by the ARM microprocessor are as follows two:

SWI Software Interrupt Instruction

Bkpt Breakpoint Interrupt Instruction

The SWI instruction format is:

Immediate number of swi{conditional}24 bit

The SWI directive is used to generate software interrupts so that the user program can invoke the system APIs of the operating system. The operating system provides the appropriate system service in the exception handler for the SWI, and the 24-bit immediate number in the instruction specifies the type of API that the user program invokes.

instruction Example:

SWI 0x02

This instruction invokes the system routine of the operating system number bit 02.

ARM instruction Set 2