ARM instruction Set-SWP directives

ARM instruction Set-SWP directives

SWP and SWPB are the atomic operations of a storage unit in an arm instruction set, that is, one-time reading of the storage unit and non-segmentation. The SWP and SWPB respectively complete a single word (32bit) and one byte (8bit) of data exchange between the memory and the register.

The SWP instruction mainly completes the synchronous operation of the ARM architecture processor, and realizes the operation of the semaphore in the Linux operating system. However, this directive is not adopted after the ARMV6 architecture, but is implemented through extended Ldrex and Strex. This article mainly introduces the function of SWP, and introduces Ldrex and Strex later.

The instruction format for SWP is as follows:

SWP {}{b} Rd, Rm, [Rn]

Where Rd is the destination register, the values read from memory are stored in this register

The Rm Register is an operand that stores the values in this register in a storage unit

[RN] is a register indirection, and Rn holds the address of a storage unit

Suppose [Rn] is stored in the semaphore, when a program to modify the semaphore, it will call the SWP instruction to complete the operation of the semaphore, that is, the memory unit read and write is an atomic operation, will not be interrupted, the execution of the command as shown in 1:

Figure 1

When multiple programs want to access their shared resources, we have to do a synchronization mechanism to keep the data safe. Typically, a shared resource can be a shared memory or an external device that accesses these resources to make the CPU, process, or thread. To complete the synchronization mechanism, an atomic variable is used to preserve the state of the resource. As shown in 2, a two-dollar semaphore (0 or 1) is used to synchronize shared resources when both process A and process B have to access the semaphore semaphore.
Span style= "Word-wrap:break-word; font-size:11.8182px; Line-height:16.3636px "> Figure 2

For a process, first access to the semaphore Semaphore Discovery State is available, the state of semaphore should be modified immediately, telling other processes that this resource is being used. However, the system can be dispatched to process B because the time slice is exactly exhausted. The discovery State is also available when process B accesses the semaphore, so modifying semaphore tells other processes that the resource is being used, and when the system is dispatched to process a again, process A does not know that process B has modified the semaphore and uses the public resources, so the last unfinished task Start modifying semaphore and start using public resources. Therefore, in this case, the signal volume is not in sync with a dummy. So if you use the SWP instruction, this is avoided by the SWP instruction, which completes the atomic operation of the memory unit once read and written.

The following assembly code is an example of implementing mutual exclusion through SWP

EXPORT LOCK_MUTEX_SWP

LOCK_MUTEX_SWP PROC

LDR R2, =locked

SWP R1, R2, [r0]; Swap R2 with location [R0], [R0] value placed in R1

CMP R1, R2; Check if memory value was ' locked '

BEQ LOCK_MUTEX_SWP; If So, retry immediately

BX LR; If not, lock successful, return

Endp

EXPORT UNLOCK_MUTEX_SWP

Unlock_mutex_swp

LDR R1, =unlocked

STR R1, [R0]; Write value ' unlocked ' to location [R0]

BX LR

Endp

Of course, in addition to the above, it is possible to interrupt the operation of the read and write due to the interruption. In some relatively simple systems, it is possible to use a non-disruptive approach in critical code to ensure atomicity of data operations, but for today's complex multitasking operating systems, the prohibition of interrupts is clearly not an effective workaround. So SWP is not required to disable interrupts through special access, but this also prolongs the response time of interrupts. With the rapid development of processors, multi-core processors have shown a strong advantage, the problem of synchronization is more obvious. As shown in 3, a system consists of a cortex-a8 and cortex-m4, and they all access a piece of storage space together.

Figure 3

SWP instructions in this mode, it is very embarrassing, if still use the original special access mode, may greatly reduce the performance of multi-core processing. So since the ARMV6 architecture, it is no longer possible to use the SWP instruction to implement synchronous functions, but rather to add Ldrex and Strex instruction completion related operations. Specific usage will be detailed in the Ldrex and Strex articles.

ARM instruction Set-SWP directives