ARM processor mode and register allocation

ARM processor status

The ARM microprocessor generally has two working states and can be switched between them:

The first type is the arm State. At this time, the processor executes the 32-bit arm command;

The second is the thumb State. At this time, the processor executes the 16-bit half-aligned thumb command.

During the execution of a program, the microprocessor can switch between the two working states at any time, and the change in the working state of the processor does not affect the working mode of the processor and the content in the corresponding register. However, the ARM microprocessor should be in the arm State when executing code.

 

ARM processor status

Entering the thumb state: When the status bit (bit 0) of the operand register is 1, you can run the Bx command,
Enables the microprocessor to switch from arm to thumb. In addition, when the processor is in the thumb state, an exception (such as IRQ, Fiq, UNDEF, abort, and SWI) occurs
When an exception is returned, it is automatically switched to the thumb status.

Enter the arm status: When the status bit of the operand register is 0, the microprocessor can switch from the thumb status to the arm status when the Bx command is executed. In addition, when the processor performs Exception Processing, it puts the PC pointer into the exception Mode Link register and starts to execute the program from the exception vector address, which can also switch the processor to the arm state.

 

ARM processor Mode

ARM microprocessor supports seven operating modes:

User Mode (usr): The normal program execution status of the ARM processor.

Fast interrupt mode (FIQ): used for high-speed data transmission or channel processing.

External Interrupt mode (IRQ): used for general interrupt processing.

Management Mode (SVC): The protection mode used by the operating system.

Data Access termination mode (ABT): This mode is used to protect virtual storage and storage when data or command prefetch is terminated.

System Mode (sys): runs privileged operating system tasks.

Define command stop mode (UND): This mode is used to support software simulation of hardware coprocessor when undefined commands are executed.

 

The ARM microprocessor has 37 32-bit registers, 31 of which are general-purpose registers and 6 are status registers. However, these registers cannot be accessed at the same time, depending on which registers are programmable.
The working status and specific running mode of the microprocessor. But at any time, the general register R14 ~ R0, program counter PC, one or two status registers are accessible.

1. Register Organization in arm working state


General registers:
General registers include R0 ~ R15 can be divided into three types:
-Ungrouped register R0 ~ R7;
-Grouping register R8 ~ R14
-Program counter PC (R15)
Ungrouped register R0 ~ R7:
In all running modes, ungrouped registers point to the same physical register, which is not used by the system for special purposes. Therefore, during the interruption or Exception Processing for running mode conversion, because the same physical registers are used in different processor running modes, data in the registers may be damaged. This should be noted during programming.
Grouping register R8 ~ R14
For Grouping registers, the physical registers they access each time are related to the current operating mode of the processor.
For R8 ~ FOR R12, each register corresponds to two different physical registers. When the FIQ mode is used, the access register r8_fiq ~ R12_fiq; when using modes other than FIQ, the access register r8_usr ~ R12_usr.
For R13 and R14, each register corresponds to six different physical registers, one of which is shared by the user mode and the system mode, the other five physical registers correspond to the other five different operating modes.
The following mark is used to identify different physical registers:
R13 _ <mode>
R14_< mode>
Mode is one of the following modes: USR, Fiq, IRQ, SVC, Abt, and und.
Register R13 is often used as a stack pointer in arm commands, but this is just a habit. You can also use other registers as a stack pointer. In the thumb instruction set, some instructions require the use of R13 as a stack pointer.

Since each running mode of the processor has its own physical register R13, in the initialization part of the user application, it is generally necessary to initialize R13 in each mode, empty stack pointing to this running mode
In this way, when the program runs into the exception mode, you can put the register to be protected into the stack pointed to by R13, and when the program returns from the exception mode, this method is used to recover from the corresponding stack.
This ensures normal execution of the program after an exception occurs.
R14 is also called the subroutine Link
Register) or connection register LR. When executing the BL subroutine call command, R15 (program counter PC) is backed up in R14. In other cases, R14 is used as a general register. And
Similarly, when an interrupt or exception occurs, the corresponding grouping registers r14_svc, r14_irq, r14_fiq, r14_abt, and r14_und are used to save the R15 response.
Value.
Register R14 is commonly used in the following situations:
In each running mode, R14 can be used to save the return address of the subprogram. When the subprogram is called using the BL or blx command, the current value of the PC is copied to R14, after the subroutine is executed, copy the R14 value back to the PC to complete the return of the subroutine call. The preceding instructions are available:
1. execute any of the following commands:
MoV PC, LR
BX lR
2. Use the following command at the subprogram entrance to store R14 into the stack:
Stmfd SP !, {<Regs>, LR}
The following command can be used to return the subprogram:
Ldmfd SP !, {<Regs>, PC}
R14 can also be used as a general register.
Program counter PC (R15)

Register R15 is used as a program counter (PC ). In the arm status, the bit [1:0] is 0, and the bit [31: 2] is used to save the PC. In the thumb status, the bit [0] is 0, and the bit
[31: 1] It is used to save the PC. Although it can be used as a general register, some commands have some special restrictions when using R15. If you do not pay attention, the execution results will be unpredictable. In arm status
Under, the 0 and 1 bits of the PC are 0, and in the thumb state, the 0 bits of the PC are 0.
Although R15 can also be used as a general register, it is generally not used in this way, because there are some special restrictions on the use of R15. When these restrictions are violated, the execution results of the program are unknown.
Because the ARM architecture uses multi-level pipeline technology, for the arm instruction set, the PC always points to the address of the next two instructions of the current command, that is, the value of PC is the address value of the current command plus 8 bytes.

In the arm state, you can access 16 General registers and one or two State registers discussed above at any time. In non-user mode (privileged mode), you can access a specific mode grouping register. Figure 2.3 shows which registers are accessible in each mode.
Register R16:
Register R16 is used as CPSR (current Program Status Register, current Program Status Register), CPSR can be accessed in any running mode, it includes the condition flag, the interrupt prohibition bit, the current processor mode flag bit, and some other related control and status bit.
Each running mode has a dedicated physical status register called spsr (saved Program Status Register, backup program Status Register). When an exception occurs, spsr is used to save the current CPSR value. When an exception exits, spsr can restore CPSR.
Since user mode and system mode are not in exception mode, they do not have spsr. When you access spsr in both modes, the results are unknown.
Ii. Register Organization in the thumb operating state



The register set in the thumb state is a subset of the register set in the arm State. The program can directly access eight general-purpose registers (r7 ~ R0), program counter (PC), stack pointer (SP ),
The connection registers (LR) and CPSR. At the same time, each privileged mode has a group of SP, LR, and spsr. Figure 2.4 shows the register organization in the thumb state.

The relationship between the register organization in the thumb state and the register organization in the arm state:
-R0 ~ In the thumb and arm States ~ R7 is the same.
-CPSR In the thumb state is the same as that in the arm state.
-The SP in the thumb State corresponds to the R13 in the arm state.
-LR in the thumb State corresponds to R14 in the arm state.
-The program counter in the thumb State corresponds to the R15 in the arm state.
As shown in Figure 2.5:

Access the high register (hi-registers) in the thumb status ):

In the thumb status, the high register R8 ~ R15 is not part of the standard register set, but it can be accessed by using assembler programs with limited limitations and used as a fast temporary register. Use band special
MoV commands for special variables, data can be transmitted between the low register and the high register; the value of the high register can be compared using the CMP and add commands or added with the value in the low register.

Program Status Register
The ARM architecture contains one current Program Status Register (CPSR) and five backup program status registers (spsrs ). The backup program status register is used for exception handling. Its functions include:
-Save the current operation information in ALU
-Control the permission and prohibition of interruptions
-Set the running mode of the processor.
The arrangement of each bit of the Program Status Register is shown in Figure 2.6:

Condition code flags)
N, Z, C, and V are condition code signs. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether a command is executed.
In the arm State, most commands are executed with conditions.
In the thumb state, only branch commands are executed with conditions.