Arm instruction suffix and common read instruction

I. Optional instruction suffixes

"S" Suffix: The instruction uses the "S" suffix. After the instruction is executed, the condition flag of the Status Register will be refreshed. If the "S" suffix is not used, the condition flag of the Status Register does not change after the command is executed. This flag is often used to test conditions, for example, whether to overflow or carry. Based on these changes, you can determine whether the flag is greater than or equal, this may affect the command execution sequence.

"!" Suffix

If the command address expression does not contain "!", The address in the base address register does not change. If the instruction contains a suffix, the result is as follows:

Value in base address register (after instruction execution) = value before instruction execution + address offset

Note:

"!" The suffix must be followed by the address expression, and the address expression must have a clear address offset.

"!" The suffix cannot be used after R15 (PC ).

When used after a single register, it must be confirmed that this register has a recessive offset. For example: "analytic dB SP !, {R3, R5, R7} "the implicit offset of the address base register SP is 4.

II. Specific instructions

LDR/STR data loading/storage commands

Ldrb/strb bytes data loading/storage commands

Ldrh/strh half-character data loading/storage commands

Eg: LDR R4, start; read the word data with the storage address "start" into r4

LDR r0, [R1]; read the word data with the storage address R1 into R0

LDR r0, [R1, R2]; read the word data with the storage address R1 + R2 into R0

LDR r0, [R1, #8]; read the word data with the storage address R1 + 8 into R0

LDR r0, [R1, R2, LSL #2]; read the word data with the storage address R1 + R2 <2 to R0

STR R5, data1; store R5 to data1

Similarly, we can determine the meaning expressed by other STR forms.

The load-store command is used for data transmission between memory and processor registers.

Load is used to load data in memory into registers.

Store stores the register data in the memory.

Note: ldrr5, [R6, #0x04]! Use R6 + 4 as the address. After data transmission is completed.

LDR R5, [R6], #0x04 uses R6 as the address. After data transmission is complete, R6 = R6 + 4

 

Stmfdsp !, {R0-R4} presses data in the R0-R4 into the stack, and R13 is the stack pointer.

Ldmfdsp !, {R0-R4} pulls data out of the stack and restores the value of the R0-R4.

 

DCD is used to allocate memory units of a certain segment, and initializes the memory allocated by the. DCD pseudocommand with expr in the pseudo command. The memory needs to be aligned with words, which can be used to define data tables or other constants.

Eg: Data DCD, 6 data points to the starting address of the memory, the memory is 3 units, and the content is 4, 5, 6.

Note that the number is equivalent to a constant, so in LDR r0, data, the content in R0 is the value of data.

 

LR is the R14 in arm, the subprogram link register, SP is the R13 Stack pointer register in arm, R15 is the PC, and the program counter.

When executing the BL subroutine call command, R15 (program counter PC) is backed up in R14.

Read Status Register commands. In the ARM processor, only the Mrs commands can be read from the State Register CPSR or spsr to the General Register. The command format is as follows;

Write Status Register commands. In the ARM processor, only MSR commands can be directly set as follows:

Spsr is a register used to back up CPSR. When an exception occurs, spsr automatically backs up the CPSR in the previous State to restore the previous State later.