Arm I/O access problems (dcache enabling and MMU not enabling problems)

 

Today, debugging has encountered a particularly strange problem. It is difficult to use serial port sending,CodeIt is like this:

 

If (flag in memory mapped REG ){

Write Char to transmit Reg

}

 

Something sent from the serial port is always wrong. JTAG debugging found that the single step is correct, but an error occurs as long as it runs at full speed.

 

After thinking about it, it seems that it is wrong to read the flag back, but how is it possible ??

 

After careful consideration, I found a problem. How does arm know to read this address to obtain the flag every time?

Although the address of memory-mapped Reg has been defined as volatile, but this only tells GCC not to be optimized into the register,

Arm can also read data from the cache. Arm does not have dedicated Io commands. How can we make it necessary to read the memory address?

 

There are two answers:

1) Disable D-Cache

2) Enable D-Cache and MMU, configure MMU, and set the memory ing Register address to none-cached

 

I opened the D-cache, but did not enable MMU. The result is that I am porting the operating system to the lowest layer,

I want to enable D-cache to increase the speed and enable it, but my operating system does not use MMU, and I am too lazy to configure MMU for direct ing,

I just disabled it. The result is miserable !! You can pay more attention to things in the future.