ARM microprocessor instruction set Overview (I) -- Detailed notes on ARM application system development

ARM microprocessor instruction set Overview

The arm instruction set is load/storage-type. That is to say, the instruction set can only process the data in the register, and the processing results must be put back into the register, access to the system memory requires special loading/storage commands.

ARM microprocessor instruction sets can be divided into six categories

Jump command, data processing command,ProgramStatus Register (SRS) processes commands, load/storage commands, coprocessor commands, and abnormal generation commands.

1. Condition field of the Instruction

When the processor is in the arm State, almost all commands are executed conditionally according to the condition code status in cpsr and the condition domain of the command. When the execution conditions of the command are met, the command is executed. Otherwise, the command is ignored. Each arm command contains a four-digit condition code, which is located at a maximum of four [31: 28] digits. There are 16 condition codes. Each condition code can be expressed by two characters. These two characters can be added to the end of the command mnemonic and used together with the command.
For example, if the suffix EQ is changed to beq, the jump command B can be added to indicate that "jump is equal", that is, a jump occurs when the Z mark in CPSR is set.

Of the 16 condition flag types, only 15 can be used.

2. Addressing of arm instructions: immediate addressing

Immediate addressing is also called immediate addressing. This is a special addressing method. The operand itself is given in the instruction, and the operand is obtained as long as the instruction is taken out.

Register addressing

Register addressing uses the value in the register as the operand.

Register indirect addressing

The indirect addressing of registers is to use the value in registers as the address of the operand, And the operand itself is stored in the memory.

Base Address addressing

Base Address addressing is to add the content of the register (usually called the base address register) to the address offset given in the instruction to obtain a valid address of an operand. Address Change Addressing is often used to access address units near a base address. Example:

LDR r0, [R1, #4]; R0 1_[ R1 + 4]
LDR r0, [R1, #4]! ; R0 1_[ R1 + 4], R1 1_r1 + 4
LDR r0, [R1], #4; R0 1_[ R1], R1 1_r1 + 4
LDR r0, [R1, R2]; R0 1_[ R1 + R2]

Multi-register addressing

Using Multi-register addressing, one instruction can transmit multiple register values. This addressing method can be used to transmit a maximum of 16 general register values. Example

Ldmia r0, {R1, R2, R3, R4}
; R1 limit [R0]
; R2 limit [R0 + 4]
; R3 limit [R0 + 8]
; R4 limit [R0 + 12]

Relative addressing

Similar to the base address addressing mode, the relative addressing is based on the current value of the program counter PC, and the address label in the instruction is used as the offset to get the valid address of the operand after adding the two.
BL next; jump to the subprogram next and execute

Stack addressing

The ARM microprocessor supports four types of stack operations:
-Full incremental Stack: the stack pointer points to the last pushed data and is generated from the low address to the high address.
-Full decline Stack: the stack pointer points to the last pushed data and is generated from the high address to the low address.
-Empty increment Stack: the stack pointer points to the next empty location of the data to be placed and is generated from the low address to the high address.
-Empty decline Stack: the stack pointer points to the next empty location of the data to be placed and is generated from the high address to the low address.